/*-------------------------------------------------------------------------------------
//	Copyright (c) 2022 by Hailotech This model is the confidential and
//	proprietary property of Hailotech and the possession or use of this
//	file requires a written license from Hailotech.
-------------------------------------------------------------------------------------*/



#include <stdint.h>

#ifndef DRAM_DMA_PACKAGE_MACROS_H
#define DRAM_DMA_PACKAGE_MACROS_H

/* HW constants and parameters for package "dram_dma" */

#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__N_AXI_QOS_BITS (3)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__N_CH (32)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__N_CH_RX_CREDIT (4096)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__N_CH_TX_CREDIT (2048)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__N_DD_DESC (16)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__N_DESC (16)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__N_DIR_CH (16)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__N_DM_DESC (16)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__N_ENHANCED_CH (4)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__N_FULL_PATTERN (4)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__N_MAX_PATTERNS (4)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__N_PATTERNS_MAX_LINES (262144)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__N_PATTERNS_MAX_PAGES (262144)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__N_REGULAR_CH (12)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__N_RX_SHMIFO (24)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__N_SD_DESC (16)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__N_SIMP_PATTERN (12)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__N_SM_DESC (16)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__N_SW_CH (16)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__N_SW_INT (4)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__N_TX_SHMIFO (20)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__PAGE_SIZE_MAX (13)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__PAGE_SIZE_MAX_8B (10)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__W_BURST_SIZE (29)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__W_BURST_SIZE_8B (26)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__W_C2C_SEL (6)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__W_CCB_DESC_INDEX (18)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__W_CCB_DESC_INDEX_LOG (5)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__W_CFG_DATA (32)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__W_CH (5)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__W_CH_CREDIT_SIZE (10)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__W_CH_RX_CREDIT (13)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__W_CH_TX_CREDIT (12)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__W_CORE_ADDR (35)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__W_CORE_BASE_ADDR (29)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__W_CSR_CFG_ADDR (13)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__W_DDR_ADDR (35)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__W_DDR_BASE_ADDR (26)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__W_DD_DESC (4)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__W_DESC (4)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__W_DESC_DEMUX_ADDR (43)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__W_DIR_CH (4)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__W_DM_DESC (4)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__W_ENG_CFG_ADDR (14)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__W_MAX_PATTERNS (2)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__W_PATTERNS_MAX_LINES (18)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__W_PATTERNS_MAX_PAGES (18)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__W_SD_DESC (4)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__W_SHMIFO (5)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__W_SM_DESC (4)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__W_SW_CH (4)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__W_VDMA_AXI_ADDR (64)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__W_VDMA_AXI_DATA_DATA (64)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__W_VDMA_AXI_DATA_DESC (128)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__W_VDMA_AXI_ID_DATA0 (2)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__W_VDMA_AXI_ID_DATA1 (4)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__W_VDMA_AXI_ID_DESC (3)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__W_VDMA_CFG_ADDR (10)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__W_VDMA_MEM_ADDR (5)
#define DRAM_DMA_PACKAGE__DRAM_DMA_ENGINE__W_VDMA_MEM_DATA (256)
#define DRAM_DMA_PACKAGE__DRAM_DMA_WRAPPER__ADDR_ALLSTRB_OFFSET (56)
#define DRAM_DMA_PACKAGE__DRAM_DMA_WRAPPER__ADDR_APCMD_OFFSET (55)
#define DRAM_DMA_PACKAGE__DRAM_DMA_WRAPPER__FPGA_N_HW_DMA_ENG (0)
#define DRAM_DMA_PACKAGE__DRAM_DMA_WRAPPER__N_DESC_AXI (1)
#define DRAM_DMA_PACKAGE__DRAM_DMA_WRAPPER__N_DMA_ENG (4)
#define DRAM_DMA_PACKAGE__DRAM_DMA_WRAPPER__N_HMASTER (4)
#define DRAM_DMA_PACKAGE__DRAM_DMA_WRAPPER__N_HW_DMA_ENG (3)
#define DRAM_DMA_PACKAGE__DRAM_DMA_WRAPPER__N_SW_DMA_ENG (1)
#define DRAM_DMA_PACKAGE__DRAM_DMA_WRAPPER__N_TOT_DMA_DIR_CH (48)
#define DRAM_DMA_PACKAGE__DRAM_DMA_WRAPPER__N_VISION_CH (10)
#define DRAM_DMA_PACKAGE__DRAM_DMA_WRAPPER__W_CFG_ADDR (16)
#define DRAM_DMA_PACKAGE__DRAM_DMA_WRAPPER__W_CFG_DATA (32)
#define DRAM_DMA_PACKAGE__DRAM_DMA_WRAPPER__W_CSR_CFG_ADDR (12)
#define DRAM_DMA_PACKAGE__DRAM_DMA_WRAPPER__W_TOT_DMA_DIR_CH (6)


#endif /* DRAM_DMA_PACKAGE_MACROS_H */
