ros2/hailort
3
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

v4.10.0

Browse Source 
v4.10.0
This commit is contained in:
HailoRT-Automation
2022-09-28 22:49:02 +03:00
committed by GitHub
parent 8295c0685f
commit d61a3bc83f
238 changed files with 16091 additions and 5688 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
common/config_definitions.json
View File

@@ -45,7 +45,8 @@
"temperature_orange_threshold": {"size": 1, "deserialize_as": "int"},
"temperature_orange_hysteresis_threshold": {"size": 1, "deserialize_as": "int"},
"temperature_throttling_enable": {"size": 1, "deserialize_as": "bool"},
"overcurrent_monitoring_orange_threshold_enable": {"size": 1, "deserialize_as": "bool"}
"deprecated__overcurrent_monitoring_orange_threshold_enable": {"size": 1, "deserialize_as": "bool"},
"overcurrent_throttling_enable": {"size": 1, "deserialize_as": "bool"}
}
},
"control":

2
common/config_schema.json
View File

@@ -44,7 +44,7 @@
"temperature_red_hysteresis_threshold": {"$ref": "#/definitions/int8_t"},
"temperature_orange_threshold": {"$ref": "#/definitions/int8_t"},
"temperature_orange_hysteresis_threshold": {"$ref": "#/definitions/int8_t"},
"overcurrent_monitoring_orange_threshold_enable": {"type": "boolean"}
"deprecated__overcurrent_monitoring_orange_threshold_enable": {"type": "boolean"}
}
},
"control":

75
common/include/context_switch_defs.h
View File

@@ -40,6 +40,20 @@ extern "C" {
(((cluster_index) << CONTEXT_SWITCH_DEFS__PACKED_LCU_ID_CLUSTER_INDEX_SHIFT) & CONTEXT_SWITCH_DEFS__PACKED_LCU_ID_CLUSTER_INDEX_MASK)
#define CONTEXT_SWITCH_DEFS__PACKED_VDMA_CHANNEL_ID__VDMA_CHANNEL_INDEX_MASK (0x1f)
#define CONTEXT_SWITCH_DEFS__PACKED_VDMA_CHANNEL_ID__ENGINE_INDEX_MASK (0x60)
#define CONTEXT_SWITCH_DEFS__PACKED_VDMA_CHANNEL_ID__ENGINE_INDEX_SHIFT (5)
#define CONTEXT_SWITCH_DEFS__PACKED_VDMA_CHANNEL_ID__SET(dst, engine_index, vdma_channel_index) do { \
(dst) = (vdma_channel_index) | ((engine_index) << CONTEXT_SWITCH_DEFS__PACKED_VDMA_CHANNEL_ID__ENGINE_INDEX_SHIFT);\
} while (0)
#define CONTEXT_SWITCH_DEFS__PACKED_VDMA_CHANNEL_ID__READ(src, engine_index, vdma_channel_index) do {\
(engine_index) = ((src) & CONTEXT_SWITCH_DEFS__PACKED_VDMA_CHANNEL_ID__ENGINE_INDEX_MASK) >> \
CONTEXT_SWITCH_DEFS__PACKED_VDMA_CHANNEL_ID__ENGINE_INDEX_SHIFT; \
(vdma_channel_index) = ((src) & CONTEXT_SWITCH_DEFS__PACKED_VDMA_CHANNEL_ID__VDMA_CHANNEL_INDEX_MASK); \
} while (0)
#pragma pack(push, 1)
typedef struct {
uint16_t core_bytes_per_buffer;
@@ -86,6 +100,7 @@ typedef enum __attribute__((packed)) {
CONTEXT_SWITCH_DEFS__ACTION_TYPE_FETCH_CCW_BURSTS,
CONTEXT_SWITCH_DEFS__ACTION_TYPE_VALIDATE_VDMA_CHANNEL,
CONTEXT_SWITCH_DEFS__ACTION_TYPE_BURST_CREDITS_TASK_START,
CONTEXT_SWITCH_DEFS__ACTION_TYPE_DDR_BUFFERING_RESET,
/* Must be last */
CONTEXT_SWITCH_DEFS__ACTION_TYPE_COUNT
@@ -141,12 +156,12 @@ typedef struct {
typedef struct {
uint16_t descriptors_count;
uint8_t cfg_channel_number;
uint8_t packed_vdma_channel_id;
} CONTEXT_SWITCH_DEFS__fetch_cfg_channel_descriptors_action_data_t;
typedef struct {
uint16_t ccw_bursts;
uint8_t cfg_channel_number;
uint8_t config_stream_index;
} CONTEXT_SWITCH_DEFS__fetch_ccw_bursts_action_data_t;
typedef struct {
@@ -172,7 +187,7 @@ typedef struct {
} CONTEXT_SWITCH_DEFS__disable_lcu_action_data_t;
typedef struct {
uint8_t vdma_channel_index;
uint8_t packed_vdma_channel_id;
uint8_t edge_layer_direction;
bool is_inter_context;
uint8_t host_buffer_type; // CONTROL_PROTOCOL__HOST_BUFFER_TYPE_t
@@ -180,7 +195,7 @@ typedef struct {
} CONTEXT_SWITCH_DEFS__deactivate_vdma_channel_action_data_t;
typedef struct {
uint8_t vdma_channel_index;
uint8_t packed_vdma_channel_id;
uint8_t edge_layer_direction;
bool is_inter_context;
bool is_single_context_network_group;
@@ -189,7 +204,7 @@ typedef struct {
} CONTEXT_SWITCH_DEFS__validate_vdma_channel_action_data_t;
typedef struct {
uint8_t vdma_channel_index;
uint8_t packed_vdma_channel_id;
uint8_t stream_index;
uint8_t network_index;
uint32_t frame_periph_size;
@@ -199,14 +214,14 @@ typedef struct {
} CONTEXT_SWITCH_DEFS__fetch_data_action_data_t;
typedef struct {
uint8_t vdma_channel_index;
uint8_t packed_vdma_channel_id;
uint8_t stream_index;
bool is_dummy_stream;
} CONTEXT_SWITCH_DEFS__change_vdma_to_stream_mapping_data_t;
typedef struct {
uint8_t h2d_vdma_channel_index;
uint8_t d2h_vdma_channel_index;
uint8_t h2d_packed_vdma_channel_id;
uint8_t d2h_packed_vdma_channel_id;
uint8_t network_index;
uint32_t descriptors_per_frame;
uint16_t programmed_descriptors_count;
@@ -218,7 +233,7 @@ typedef struct {
} CONTEXT_SWITCH_DEFS__lcu_interrupt_data_t;
typedef struct {
uint8_t vdma_channel_index;
uint8_t packed_vdma_channel_id;
} CONTEXT_SWITCH_DEFS__vdma_dataflow_interrupt_data_t;
typedef struct {
@@ -235,7 +250,7 @@ typedef struct {
} CONTEXT_SWITCH_DEFS__wait_nms_idle_data_t;
typedef struct {
uint8_t vdma_channel_index;
uint8_t packed_vdma_channel_id;
uint8_t stream_index;
bool is_inter_context;
} CONTEXT_SWITCH_DEFS__wait_dma_idle_data_t;
@@ -250,16 +265,17 @@ typedef struct {
/* edge layers structs */
typedef struct {
uint8_t packed_vdma_channel_id;
uint8_t stream_index;
uint8_t vdma_channel_index;
CONTEXT_SWITCH_DEFS__stream_reg_info_t stream_reg_info;
CONTROL_PROTOCOL__host_buffer_info_t host_buffer_info;
uint32_t initial_credit_size;
bool is_single_context_app;
} CONTEXT_SWITCH_DEFS__activate_boundary_input_data_t;
typedef struct {
uint8_t packed_vdma_channel_id;
uint8_t stream_index;
uint8_t vdma_channel_index;
uint8_t network_index;
CONTEXT_SWITCH_DEFS__stream_reg_info_t stream_reg_info;
CONTROL_PROTOCOL__host_buffer_info_t host_buffer_info;
@@ -267,48 +283,55 @@ typedef struct {
} CONTEXT_SWITCH_DEFS__activate_inter_context_input_data_t;
typedef struct {
uint8_t packed_vdma_channel_id;
uint8_t stream_index;
uint8_t vdma_channel_index;
CONTEXT_SWITCH_DEFS__stream_reg_info_t stream_reg_info;
uint64_t host_descriptors_base_address;
uint8_t desc_list_depth;
CONTROL_PROTOCOL__host_buffer_info_t host_buffer_info;
uint32_t initial_credit_size;
uint8_t connected_d2h_packed_vdma_channel_id;
} CONTEXT_SWITCH_DEFS__activate_ddr_buffer_input_data_t;
typedef struct {
uint8_t packed_vdma_channel_id;
uint8_t stream_index;
uint8_t vdma_channel_index;
CONTEXT_SWITCH_DEFS__stream_reg_info_t stream_reg_info;
uint32_t frame_credits_in_bytes;
uint16_t desc_page_size;
CONTROL_PROTOCOL__host_buffer_info_t host_buffer_info;
} CONTEXT_SWITCH_DEFS__activate_boundary_output_data_t;
typedef struct {
uint8_t packed_vdma_channel_id;
uint8_t stream_index;
uint8_t vdma_channel_index;
uint8_t network_index;
CONTEXT_SWITCH_DEFS__stream_reg_info_t stream_reg_info;
CONTROL_PROTOCOL__host_buffer_info_t host_buffer_info;
} CONTEXT_SWITCH_DEFS__activate_inter_context_output_data_t;
typedef struct {
uint8_t packed_vdma_channel_id;
uint8_t stream_index;
uint8_t vdma_channel_index;
CONTEXT_SWITCH_DEFS__stream_reg_info_t stream_reg_info;
uint32_t frame_credits_in_bytes;
uint64_t host_descriptors_base_address;
uint16_t desc_page_size;
uint8_t desc_list_depth;
CONTROL_PROTOCOL__host_buffer_info_t host_buffer_info;
uint32_t buffered_rows_count;
} CONTEXT_SWITCH_DEFS__activate_ddr_buffer_output_data_t;
typedef union {
CONTEXT_SWITCH_DEFS__activate_boundary_input_data_t activate_boundary_input_data;
CONTEXT_SWITCH_DEFS__activate_inter_context_input_data_t activate_inter_context_input_data;
CONTEXT_SWITCH_DEFS__activate_ddr_buffer_input_data_t activate_ddr_buffer_input_data;
CONTEXT_SWITCH_DEFS__activate_boundary_output_data_t activate_boundary_output_data;
CONTEXT_SWITCH_DEFS__activate_inter_context_output_data_t activate_inter_context_output_data;
CONTEXT_SWITCH_DEFS__activate_ddr_buffer_output_data_t activate_ddr_buffer_output_data;
} CONTEXT_SWITCH_COMMON__activate_edge_layer_action_t;
typedef struct {
uint8_t channel_index;
uint8_t packed_vdma_channel_id;
uint8_t config_stream_index;
CONTROL_PROTOCOL__host_buffer_info_t host_buffer_info;
} CONTEXT_SWITCH_DEFS__activate_cfg_channel_t;
typedef struct {
uint8_t channel_index;
uint8_t packed_vdma_channel_id;
uint8_t config_stream_index;
} CONTEXT_SWITCH_DEFS__deactivate_cfg_channel_t;
#pragma pack(pop)

86
common/include/control_protocol.h
View File

@@ -35,13 +35,14 @@ extern "C" {
#define CONTROL_PROTOCOL__MAX_SERIAL_NUMBER_LENGTH (16)
#define CONTROL_PROTOCOL__MAX_PART_NUMBER_LENGTH (16)
#define CONTROL_PROTOCOL__MAX_PRODUCT_NAME_LENGTH (42)
#define CONTROL_PROTOCOL__MAX_CONTEXT_SWITCH_APPLICATIONS (8)
#define CONTROL_PROTOCOL__MAX_CONTEXT_SWITCH_APPLICATIONS (32)
#define CONTROL_PROTOCOL__MAX_NUMBER_OF_CLUSTERS (8)
#define CONTROL_PROTOCOL__MAX_CONTROL_LENGTH (1500)
#define CONTROL_PROTOCOL__MAX_TOTAL_CONTEXTS (32)
#define CONTROL_PROTOCOL__MAX_TOTAL_CONTEXTS (128)
#define CONTROL_PROTOCOL__SOC_ID_LENGTH (32)
#define CONTROL_PROTOCOL__MAX_CFG_CHANNELS (4)
#define CONTROL_PROTOCOL__MAX_NETWORKS_PER_NETWORK_GROUP (8)
#define CONTROL_PROTOCOL__MAX_VDMA_ENGINES_COUNT (3)
/* Tightly coupled with the sizeof PROCESS_MONITOR__detection_results_t
and HAILO_SOC_PM_VALUES_BYTES_LENGTH */
#define PM_RESULTS_LENGTH (24)
@@ -52,6 +53,8 @@ extern "C" {
/* Tightly coupled to HAILO_MAX_TEMPERATURE_THROTTLING_LEVELS_NUMBER */
#define MAX_TEMPERATURE_THROTTLING_LEVELS_NUMBER (4)
#define MAX_OVERCURRENT_THROTTLING_LEVELS_NUMBER (8)
#define CONTROL_PROTOCOL__MAX_NUMBER_OF_POWER_MEASUREMETS (4)
#define CONTROL_PROTOCOL__DEFAULT_INIT_SAMPLING_PERIOD_US (CONTROL_PROTOCOL__PERIOD_1100US)
#define CONTROL_PROTOCOL__DEFAULT_INIT_AVERAGING_FACTOR (CONTROL_PROTOCOL__AVERAGE_FACTOR_1)
@@ -143,7 +146,7 @@ extern "C" {
CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_CORE_IDENTIFY, true, CPU_ID_CORE_CPU)\
CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_D2H_EVENT_MANAGER_SET_HOST_INFO, false, CPU_ID_APP_CPU)\
CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_D2H_EVENT_MANAGER_SEND_EVENT_HOST_INFO, false, CPU_ID_APP_CPU)\
CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_SWITCH_APPLICATION, false, CPU_ID_CORE_CPU)\
CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_SWITCH_APPLICATION /* obsolete */, false, CPU_ID_CORE_CPU)\
CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_GET_CHIP_TEMPERATURE, false, CPU_ID_APP_CPU)\
CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_READ_BOARD_CONFIG, true, CPU_ID_APP_CPU)\
CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_WRITE_BOARD_CONFIG, true, CPU_ID_APP_CPU)\
@@ -169,6 +172,7 @@ extern "C" {
CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_CORE_PREVIOUS_SYSTEM_STATE, false, CPU_ID_CORE_CPU)\
CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_CORE_WD_ENABLE, false, CPU_ID_CORE_CPU)\
CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_CORE_WD_CONFIG, false, CPU_ID_CORE_CPU)\
CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_CONTEXT_SWITCH_CLEAR_CONFIGURED_APPS, false, CPU_ID_CORE_CPU)\
typedef enum {
#define CONTROL_PROTOCOL__OPCODE_X(name, is_critical, cpu_id) name,
@@ -353,7 +357,8 @@ typedef struct {
typedef enum {
CONTROL_PROTOCOL__HAILO8_A0 = 0,
CONTROL_PROTOCOL__HAILO8_B0,
CONTROL_PROTOCOL__HAILO8,
CONTROL_PROTOCOL__HAILO8L,
CONTROL_PROTOCOL__MERCURY_CA,
CONTROL_PROTOCOL__MERCURY_VPU,
/* Must be last!! */
@@ -877,10 +882,10 @@ typedef struct {
typedef struct {
uint8_t dynamic_contexts_count;
uint32_t host_boundary_channels_bitmap;
uint8_t cfg_channel_numbers[CONTROL_PROTOCOL__MAX_CFG_CHANNELS];
uint32_t host_boundary_channels_bitmap[CONTROL_PROTOCOL__MAX_VDMA_ENGINES_COUNT];
uint8_t power_mode; // CONTROL_PROTOCOL__power_mode_t
CONTROL_PROTOCOL__INFER_FEATURE_LIST_t infer_features;
CONTROL_PROTOCOL__VALIDATION_FEATURE_LIST_t validation_features;
uint8_t networks_count;
uint16_t batch_size[CONTROL_PROTOCOL__MAX_NETWORKS_PER_NETWORK_GROUP];
} CONTROL_PROTOCOL__application_header_t;
@@ -888,8 +893,6 @@ typedef struct {
typedef struct {
uint32_t context_switch_version_length;
uint32_t context_switch_version;
uint32_t validation_features_length;
CONTROL_PROTOCOL__VALIDATION_FEATURE_LIST_t validation_features;
uint32_t application_count_length;
uint8_t application_count;
uint32_t application_header_length;
@@ -906,7 +909,6 @@ typedef enum {
typedef struct {
CONTROL_PROTOCOL__CONTEXT_SWITCH_VERSION_t context_switch_version;
CONTROL_PROTOCOL__VALIDATION_FEATURE_LIST_t validation_features;
uint8_t application_count;
CONTROL_PROTOCOL__application_header_t application_header[CONTROL_PROTOCOL__MAX_CONTEXT_SWITCH_APPLICATIONS];
} CONTROL_PROTOCOL__context_switch_main_header_t;
@@ -969,6 +971,7 @@ typedef enum {
CONTROL_PROTOCOL__CONTEXT_SWITCH_ACTION_ADD_REPEATED,
CONTROL_PROTOCOL__CONTEXT_SWITCH_ACTION_FETCH_CCW_BURSTS,
CONTROL_PROTOCOL__CONTEXT_SWITCH_ACTION_BURST_CREDITS_TASK_START,
CONTROL_PROTOCOL__CONTEXT_SWITCH_ACTION_EDGE_LAYER_ACTIVATION_ACTIONS_POSITION,
/* must be last*/
CONTROL_PROTOCOL__CONTEXT_SWITCH_ACTION_COUNT,
@@ -1054,27 +1057,23 @@ typedef struct {
uint32_t bytes_in_pattern;
} CONTROL_PROTOCOL__host_buffer_info_t;
/* TODO: merge CONTROL_PROTOCOL__edge_layer_common_info_t into the header (HRT-7113) */
typedef struct {
uint8_t communication_type;
uint8_t edge_connection_type;
} CONTROL_PROTOCOL__edge_layer_header_t;
typedef struct {
uint8_t stream_index;
uint8_t engine_index;
uint8_t vdma_channel_index;
uint8_t stream_index;
uint8_t network_index;
CONTROL_PROTOCOL__nn_stream_config_t nn_stream_config;
} CONTROL_PROTOCOL__edge_layer_common_info_t;
typedef struct {
uint64_t host_descriptors_base_address;
uint8_t desc_list_depth;
} CONTROL_PROTOCOL__host_desc_address_info_t;
typedef struct {
CONTROL_PROTOCOL__edge_layer_common_info_t common_info;
uint32_t frame_credits_in_bytes;
uint16_t desc_page_size;
CONTROL_PROTOCOL__host_buffer_info_t host_buffer_info;
} CONTROL_PROTOCOL__network_boundary_output_t;
typedef struct {
@@ -1084,9 +1083,7 @@ typedef struct {
typedef struct {
CONTROL_PROTOCOL__edge_layer_common_info_t common_info;
uint32_t frame_credits_in_bytes;
CONTROL_PROTOCOL__host_desc_address_info_t host_desc_address_info;
uint16_t desc_page_size;
CONTROL_PROTOCOL__host_buffer_info_t host_buffer_info;
uint32_t buffered_rows_count;
} CONTROL_PROTOCOL__ddr_buffer_output_t;
@@ -1097,7 +1094,7 @@ typedef struct {
typedef struct {
CONTROL_PROTOCOL__edge_layer_common_info_t common_info;
uint16_t desc_page_size;
CONTROL_PROTOCOL__host_buffer_info_t host_buffer_info;
uint32_t initial_credit_size;
} CONTROL_PROTOCOL__network_boundary_input_t;
@@ -1109,8 +1106,10 @@ typedef struct {
typedef struct {
CONTROL_PROTOCOL__edge_layer_common_info_t common_info;
CONTROL_PROTOCOL__host_desc_address_info_t host_desc_address_info;
CONTROL_PROTOCOL__host_buffer_info_t host_buffer_info;
uint32_t initial_credit_size;
uint8_t connected_d2h_engine_index;
uint8_t connected_d2h_channel_index;
} CONTROL_PROTOCOL__ddr_buffer_input_t;
typedef struct {
@@ -1121,6 +1120,12 @@ typedef struct {
uint8_t should_use_stream_remap;
} CONTROL_PROTOCOL__stream_remap_data_t;
typedef struct {
CONTROL_PROTOCOL__host_buffer_info_t config_buffer_info;
uint8_t engine_index;
uint8_t vdma_channel_index;
} CONTROL_PROTOCOL__config_channel_info_t;
#if defined(_MSC_VER)
// TODO: warning C4200
#pragma warning(push)
@@ -1133,8 +1138,8 @@ typedef struct {
uint8_t is_last_control_per_context;
uint32_t cfg_channels_count_length;
uint8_t cfg_channels_count;
uint32_t config_buffer_infos_length;
CONTROL_PROTOCOL__host_buffer_info_t config_buffer_infos[CONTROL_PROTOCOL__MAX_CFG_CHANNELS];
uint32_t config_channel_infos_length;
CONTROL_PROTOCOL__config_channel_info_t config_channel_infos[CONTROL_PROTOCOL__MAX_CFG_CHANNELS];
uint32_t context_stream_remap_data_length;
CONTROL_PROTOCOL__stream_remap_data_t context_stream_remap_data;
uint32_t number_of_edge_layers_length;
@@ -1209,14 +1214,14 @@ typedef struct {
/* Must be first */
CONTROL_PROTOCOL__ACTION_HEADER_t header;
uint16_t descriptors_count;
uint8_t cfg_channel_handle;
uint8_t config_stream_index;
} CONTROL_PROTOCOL__READ_VDMA_ACTION_t;
typedef struct {
/* Must be first */
CONTROL_PROTOCOL__ACTION_HEADER_t header;
uint16_t ccw_bursts;
uint8_t cfg_channel_handle;
uint8_t config_stream_index;
} CONTROL_PROTOCOL__FETCH_CCW_BURSTS_ACTION_t;
typedef struct {
@@ -1283,7 +1288,9 @@ typedef struct {
typedef struct {
/* Must be first */
CONTROL_PROTOCOL__ACTION_HEADER_t header;
uint8_t h2d_engine_index;
uint8_t h2d_vdma_channel_index;
uint8_t d2h_engine_index;
uint8_t d2h_vdma_channel_index;
uint32_t descriptors_per_frame;
uint16_t programmed_descriptors_count;
@@ -1299,6 +1306,11 @@ typedef struct {
CONTROL_PROTOCOL__ACTION_HEADER_t header;
} CONTROL_PROTOCOL__BURST_CREDITS_TASK_START_ACTION_T;
typedef struct {
/* Must be first */
CONTROL_PROTOCOL__ACTION_HEADER_t header;
} CONTROL_PROTOCOL__EDGE_LAYER_ACTIVATION_ACTIONS_POSITION_MARKER_T;
typedef struct {
CONTROL_PROTOCOL__TRIGGER_t trigger;
uint16_t triggers_action_count;
@@ -1360,6 +1372,8 @@ typedef struct {
uint8_t application_index;
uint32_t dynamic_batch_size_length;
uint16_t dynamic_batch_size;
uint32_t keep_nn_config_during_reset_length;
uint8_t keep_nn_config_during_reset;
} CONTROL_PROTOCOL__change_context_switch_status_request_t;
typedef struct {
@@ -1371,13 +1385,6 @@ typedef struct {
uint8_t interrupt_sub_index;
} CONTROL_PROTOCOL__set_dataflow_interrupt_request_t;
typedef struct {
uint32_t application_index_length;
uint8_t application_index;
uint32_t dynamic_batch_size_length;
uint16_t dynamic_batch_size;
} CONTROL_PROTOCOL__switch_application_request_t;
typedef struct {
uint32_t connection_type_length;
uint8_t connection_type;
@@ -1429,6 +1436,8 @@ typedef struct {
CONTROL_PROTOCOL_fuse_info_t fuse_info;
uint32_t pd_info_length;
uint8_t pd_info[PM_RESULTS_LENGTH];
uint32_t partial_clusters_layout_bitmap_length;
uint32_t partial_clusters_layout_bitmap;
} CONTROL_PROTOCOL__get_extended_device_information_response_t;
/* Tightly coupled to hailo_throttling_level_t */
@@ -1446,8 +1455,8 @@ typedef struct {
uint8_t current_overcurrent_zone;
uint32_t red_overcurrent_threshold_length;
float32_t red_overcurrent_threshold;
uint32_t orange_overcurrent_threshold_length;
float32_t orange_overcurrent_threshold;
uint32_t overcurrent_throttling_active_length;
bool overcurrent_throttling_active;
uint32_t temperature_throttling_active_length;
bool temperature_throttling_active;
uint32_t current_temperature_zone_length;
@@ -1464,6 +1473,10 @@ typedef struct {
int32_t red_temperature_threshold;
uint32_t red_hysteresis_temperature_threshold_length;
int32_t red_hysteresis_temperature_threshold;
uint32_t requested_overcurrent_clock_freq_length;
uint32_t requested_overcurrent_clock_freq;
uint32_t requested_temperature_clock_freq_length;
uint32_t requested_temperature_clock_freq;
} CONTROL_PROTOCOL__get_health_information_response_t;
typedef enum {
@@ -1659,7 +1672,6 @@ typedef union {
CONTROL_PROTOCOL__d2h_event_manager_send_host_info_event_request_t d2h_event_manager_send_host_info_event_request;
CONTROL_PROTOCOL__read_board_config_request_t read_board_config_request;
CONTROL_PROTOCOL__write_board_config_request_t write_board_config_request;
CONTROL_PROTOCOL__switch_application_request_t switch_application_request;
CONTROL_PROTOCOL__config_context_switch_breakpoint_request_t config_context_switch_breakpoint_request;
CONTROL_PROTOCOL__get_context_switch_breakpoint_status_request_t get_context_switch_breakpoint_status_request;
CONTROL_PROTOCOL__enable_debugging_request_t enable_debugging_request;
@@ -1713,7 +1725,7 @@ typedef struct {
bool is_first_control_per_context;
bool is_last_control_per_context;
uint8_t cfg_channels_count;
CONTROL_PROTOCOL__host_buffer_info_t config_buffer_infos[CONTROL_PROTOCOL__MAX_CFG_CHANNELS];
CONTROL_PROTOCOL__config_channel_info_t config_channel_infos[CONTROL_PROTOCOL__MAX_CFG_CHANNELS];
CONTROL_PROTOCOL__stream_remap_data_t context_stream_remap_data;
uint8_t number_of_edge_layers;
uint8_t number_of_trigger_groups;

4
common/include/d2h_events.h
View File

@@ -102,10 +102,10 @@ typedef struct {
typedef struct {
uint32_t overcurrent_zone;
float32_t exceeded_alert_threshold;
float32_t sampled_current_during_alert;
bool is_last_overcurrent_violation_reached;
} D2H_EVENT_health_monitor_overcurrent_alert_event_message_t;
#define D2H_EVENT_HEALTH_MONITOR_OVERCURRENT_ALERT_EVENT_PARAMETER_COUNT (2)
#define D2H_EVENT_HEALTH_MONITOR_OVERCURRENT_ALERT_EVENT_PARAMETER_COUNT (4)
/* D2H_EVENT_health_monitor_lcu_ecc_error_event_message_t should be the same as hailo_health_monitor_lcu_ecc_error_notification_message_t */
typedef struct {

27
common/include/firmware_status.h
View File

@@ -108,6 +108,9 @@ Updating rules:
FIRMWARE_STATUS__X(HAILO_STATUS_UPDATE_CLOCK_CORE_CPU_FAILED)\
FIRMWARE_STATUS__X(HAILO_STATUS_CONTROL_ETH_INIT_FAILED)\
FIRMWARE_STATUS__X(HAILO_STATUS_SEMAPHORE_INIT_FAILED)\
FIRMWARE_STATUS__X(HAILO_STATUS_DRAM_DMA_SERVICE_INIT_FAILED)\
FIRMWARE_STATUS__X(HAILO_STATUS_VDMA_SERVICE_INIT_FAILED)\
FIRMWARE_STATUS__X(HAILO_STATUS_ERROR_HANDLING_STACK_OVERFLOW)\
\
FIRMWARE_MODULE__X(FIRMWARE_MODULE__DATAFLOW)\
FIRMWARE_STATUS__X(HAILO_DATAFLOW_STATUS_INVALID_PARAMETER)\
@@ -399,6 +402,8 @@ Updating rules:
FIRMWARE_STATUS__X(CONTROL_PROTOCOL_STATUS_INVALID_CFG_CHANNELS_COUNT_LENGTH)\
FIRMWARE_STATUS__X(CONTROL_PROTOCOL_STATUS_INVALID_DYNAMIC_BATCH_SIZE_LENGTH)\
FIRMWARE_STATUS__X(CONTROL_PROTOCOL_STATUS_INVALID_INFER_FEATURES_LENGTH) /* DEPRECATED */\
FIRMWARE_STATUS__X(CONTROL_PROTOCOL_STATUS_INVALID_CONFIG_CHANNEL_INFOS)\
FIRMWARE_STATUS__X(CONTROL_PROTOCOL_STATUS_INVALID_IS_BATCH_SIZE_FLOW_LENGTH)\
\
FIRMWARE_MODULE__X(FIRMWARE_MODULE__POWER_MEASUREMENT)\
FIRMWARE_STATUS__X(HAILO_POWER_MEASUREMENT_STATUS_POWER_INIT_ERROR)\
@@ -735,6 +740,11 @@ Updating rules:
FIRMWARE_STATUS__X(CONTEXT_SWITCH_STATUS_INVALID_CFG_CHANNELS_COUNT)\
FIRMWARE_STATUS__X(CONTEXT_SWITCH_STATUS_INVALID_HOST_BUFFER_TYPE)\
FIRMWARE_STATUS__X(CONTEXT_SWITCH_STATUS_BURST_CREDITS_TASK_IS_NOT_IDLE)\
FIRMWARE_STATUS__X(CONTEXT_SWITCH_STATUS_KERNEL_COUNT_OVERFLOW)\
FIRMWARE_STATUS__X(CONTEXT_SWITCH_STATUS_INVALID_CONFIG_STREAM_INDEX)\
FIRMWARE_STATUS__X(CONTEXT_SWITCH_STATUS_ADD_ACTION_TO_BATCH_SWITCH_BUFFER_REACHED_FORBIDDEN_MEMORY_SPACE)\
FIRMWARE_STATUS__X(CONTEXT_SWITCH_TASK_STATUS_WAIT_FOR_INTERRUPT_INTERRUPTED_BY_BATCH_CHANGE_REQUEST)\
FIRMWARE_STATUS__X(CONTEXT_SWITCH_STATUS_CANT_CLEAR_CONFIGURED_APPS_WHILE_ACTIVATED)\
\
FIRMWARE_MODULE__X(FIRMWARE_MODULE__D2H_EVENT_MANAGER)\
FIRMWARE_STATUS__X(HAILO_D2H_EVENT_MANAGER_STATUS_MESSAGE_HIGH_PRIORITY_QUEUE_CREATE_FAILED)\
@@ -774,7 +784,7 @@ Updating rules:
FIRMWARE_STATUS__X(HEALTH_MONITOR_QUEUEING_OVERCURRENT_MESSAGE_FAILED)\
FIRMWARE_STATUS__X(HEALTH_MONITOR_QUEUEING_CORE_RESET_MESSAGE_FAILED)\
FIRMWARE_STATUS__X(HEALTH_MONITOR_QUEUEING_SOFT_RESET_MESSAGE_FAILED)\
FIRMWARE_STATUS__X(HEALTH_MONITOR_INVALID_OVERCURRENT_OVERCURRENT_ZONE)\
FIRMWARE_STATUS__X(HEALTH_MONITOR_INVALID_OVERCURRENT_OVERCURRENT_ZONE) /* DEPRECATED -*/\
FIRMWARE_STATUS__X(HEALTH_MONITOR_INVALID_MESSAGE_TYPE)\
FIRMWARE_STATUS__X(HEALTH_MONITOR_INVALID_TEMPERATURE_ALARM_TYPE) /* DEPRECATED - See TEMPERATURE_PROTECTION */\
FIRMWARE_STATUS__X(HEALTH_MONITOR_SETUP_SAFETY_INTERRUPTS_FAILED)\
@@ -843,7 +853,7 @@ Updating rules:
FIRMWARE_STATUS__X(GPIO_BAD_PINMUX_GROUP)\
\
FIRMWARE_MODULE__X(FIRMWARE_MODULE__OVERCURRENT_PROTECTION)\
FIRMWARE_STATUS__X(OVERCURRENT_PROTECTION_INVALID_ALERT_THRESHOLD_VALUE)\
FIRMWARE_STATUS__X(OVERCURRENT_PROTECTION_INVALID_ALERT_THRESHOLD_VALUE) /* DEPRECATED */\
FIRMWARE_STATUS__X(OVERCURRENT_PROTECTION_INVALID_SAMPLING_PERIOD_VALUE)\
FIRMWARE_STATUS__X(OVERCURRENT_PROTECTION_INVALID_AVERAGING_FACTOR_VALUE)\
FIRMWARE_STATUS__X(OVERCURRENT_PROTECTION_UNSUPPORTED_SENSOR_TYPE)\
@@ -851,7 +861,7 @@ Updating rules:
FIRMWARE_STATUS__X(OVERCURRENT_PROTECTION_ALREADY_ACTIVE)\
FIRMWARE_STATUS__X(OVERCURRENT_PROTECTION_IS_NOT_ACTIVE)\
FIRMWARE_STATUS__X(OVERCURRENT_PROTECTION_INVALID_BOARD_CONFIG_VALUES)\
FIRMWARE_STATUS__X(OVERCURRENT_PROTECTION_NULL_POINTER_PASSED)\
FIRMWARE_STATUS__X(OVERCURRENT_PROTECTION_NULL_POINTER_PASSED) /* DEPRECATED */\
\
FIRMWARE_MODULE__X(FIRMWARE_MODULE__POWER)\
FIRMWARE_STATUS__X(POWER_INVALID_CONVERSION_TYPE)\
@@ -908,6 +918,7 @@ Updating rules:
FIRMWARE_STATUS__X(DDR_BUFFER_STATUS_TRYING_TO_CHANGE_STATE_TO_INFER_WHILE_ALREADY_DURING_INFER)\
FIRMWARE_STATUS__X(DDR_BUFFER_STATUS_NO_DDR_PAIRS_TO_RUN_INFER_ON)\
FIRMWARE_STATUS__X(DDR_BUFFER_STATUS_INFER_REACHED_TIMEOUT)\
FIRMWARE_STATUS__X(DDR_BUFFER_STATUS_OVERFLOW_IN_DESCRIPTORS_PER_BATCH)\
\
FIRMWARE_MODULE__X(FIRMWARE_MODULE__PL320)\
FIRMWARE_STATUS__X(PL320_MAILBOX_BUSY)\
@@ -984,6 +995,8 @@ Updating rules:
FIRMWARE_STATUS__X(VDMA_SERVICE_STATUS_INITIAL_DESC_BIGGER_THAN_TOTAL)\
FIRMWARE_STATUS__X(VDMA_SERVICE_STATUS_INVALID_INITIAL_CREDIT_SIZE)\
FIRMWARE_STATUS__X(VDMA_SERVICE_STATUS_TOO_LARGE_BYTES_IN_PATTERN)\
FIRMWARE_STATUS__X(VDMA_SERVICE_STATUS_INVALID_ENGINE_INDEX)\
FIRMWARE_STATUS__X(VDMA_SERVICE_STATUS_INVALID_CONSTANTS)\
\
FIRMWARE_MODULE__X(FIRMWARE_MODULE__MEMORY_LOGGER)\
FIRMWARE_STATUS__X(MEMORY_LOGGER_STATUS_DEBUG_INSUFFICIENT_MEMORY)\
@@ -1007,6 +1020,13 @@ Updating rules:
FIRMWARE_STATUS__X(DRAM_DMA_SERVICE_TOTAL_DESCS_COUNT_MUST_BE_POWER_OF_2)\
FIRMWARE_STATUS__X(DRAM_DMA_SERVICE_INVALID_DESCS_COUNT)\
FIRMWARE_STATUS__X(DRAM_DMA_SERVICE_DESC_PER_INTERRUPT_NOT_IN_MASK)\
FIRMWARE_STATUS__X(DRAM_DMA_SERVICE_STATUS_INVALID_ENGINE_INDEX)\
FIRMWARE_STATUS__X(DRAM_DMA_SERVICE_STATUS_INVALID_QM_INDEX)\
FIRMWARE_STATUS__X(DRAM_DMA_SERVICE_STATUS_INVALID_CHANNEL_TYPE)\
FIRMWARE_STATUS__X(DRAM_DMA_SERVICE_STATUS_INVALID_PERIPH_BYTES_PER_BUFFER)\
FIRMWARE_STATUS__X(DRAM_DMA_SERVICE_STATUS_INVALID_BYTES_IN_PATTERN)\
FIRMWARE_STATUS__X(DRAM_DMA_SERVICE_STATUS_INVALID_STREAM_INDEX)\
FIRMWARE_STATUS__X(DRAM_DMA_SERVICE_STATUS_INVALID_CHANNEL_INDEX)\
\
FIRMWARE_MODULE__X(FIRMWARE_MODULE__NN_CORE_SERVICE)\
FIRMWARE_STATUS__X(NN_CORE_SERVICE_STATUS_INVALID_ARG_PASSED)\
@@ -1020,6 +1040,7 @@ Updating rules:
FIRMWARE_STATUS__X(DATA_STREAM_WRAPPER_STATUS_INVALID_STREAM_INDEX)\
FIRMWARE_STATUS__X(DATA_STREAM_MANAGER_STATUS_INVALID_CREDIT_TYPE)\
FIRMWARE_STATUS__X(DATA_STREAM_MANAGER_WRAPPER_STATUS_INVALID_HOST_BUFFER_TYPE)\
FIRMWARE_STATUS__X(DATA_STREAM_MANAGER_STATUS_BATCH_CREDITS_OVERFLOW)\
\
FIRMWARE_MODULE__X(FIRMWARE_MODULE__BURST_CREDITS_TASK)\
FIRMWARE_STATUS__X(BURST_CREDITS_TASK_STATUS_TRYING_TO_ADD_ACTION_WHILE_NOT_IN_IDLE_STATE)\

3
common/include/md5.h
View File

@@ -30,7 +30,8 @@
/** Start of modifications for the open source file. **/
#include "stdint.h"
typedef uint8_t MD5_SUM_t[16];
#define MD5_DIGEST_LENGTH 16
typedef uint8_t MD5_SUM_t[MD5_DIGEST_LENGTH];
/* Any 32-bit or wider unsigned integer data type will do */
typedef size_t MD5_u32plus;
/** End of modifications. **/

13
common/include/user_config_common.h
View File

@@ -69,6 +69,19 @@ typedef enum {
SOC__NN_CLOCK_100MHz = 100 * 1000 * 1000
} SOC__NN_CLOCK_HZ_t;
typedef enum {
SOC__CPU_CLOCK_200MHz = SOC__NN_CLOCK_400MHz >> 1,
SOC__CPU_CLOCK_187MHz = SOC__NN_CLOCK_375MHz >> 1,
SOC__CPU_CLOCK_175MHz = SOC__NN_CLOCK_350MHz >> 1,
SOC__CPU_CLOCK_162MHz = SOC__NN_CLOCK_325MHz >> 1,
SOC__CPU_CLOCK_150MHz = SOC__NN_CLOCK_300MHz >> 1,
SOC__CPU_CLOCK_137MHz = SOC__NN_CLOCK_275MHz >> 1,
SOC__CPU_CLOCK_125MHz = SOC__NN_CLOCK_250MHz >> 1,
SOC__CPU_CLOCK_112MHz = SOC__NN_CLOCK_225MHz >> 1,
SOC__CPU_CLOCK_100MHz = SOC__NN_CLOCK_200MHz >> 1,
SOC__CPU_CLOCK_50MHz = SOC__NN_CLOCK_100MHz >> 1
} SOC__CPU_CLOCK_HZ_t;
typedef enum {
WD_SERVICE_MODE_HW_SW = 0,
WD_SERVICE_MODE_HW_ONLY,

14
common/include/utils.h
View File

@@ -99,6 +99,18 @@
PP_HASCOMMA(PP_COMMA __VA_ARGS__ ()),\
PP_NARG_(__VA_ARGS__, PP_RSEQ_N()))
#define PP_ISEMPTY(...) \
_PP_ISEMPTY( \
PP_HASCOMMA(__VA_ARGS__), \
PP_HASCOMMA(PP_COMMA __VA_ARGS__), \
PP_HASCOMMA(__VA_ARGS__ (/*empty*/)), \
PP_HASCOMMA(PP_COMMA __VA_ARGS__ (/*empty*/)) \
)
#define PP_PASTE5(_0, _1, _2, _3, _4) _0 ## _1 ## _2 ## _3 ## _4
#define _PP_ISEMPTY(_0, _1, _2, _3) PP_HASCOMMA(PP_PASTE5(_PP_IS_EMPTY_CASE_, _0, _1, _2, _3))
#define _PP_IS_EMPTY_CASE_0001 ,
#define UNUSED0(...)
#define UNUSED1(x) (void)(x)
#define UNUSED2(x,y) (void)(x),(void)(y)
@@ -111,4 +123,6 @@
#define ALL_UNUSED_IMPL(nargs) ALL_UNUSED_IMPL_(nargs)
#define ALL_UNUSED(...) ALL_UNUSED_IMPL( PP_NARG(__VA_ARGS__))(__VA_ARGS__ )
#define MICROSECONDS_IN_MILLISECOND (1000)
#endif /* __UTILS_H__ */