1774 lines
70 KiB
C
1774 lines
70 KiB
C
/**
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* Copyright (c) 2020-2022 Hailo Technologies Ltd. All rights reserved.
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* Distributed under the MIT license (https://opensource.org/licenses/MIT)
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**/
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/**
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* @file control_protocol.h
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* @brief Defines control protocol.
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**/
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#ifndef __CONTROL_PROTOCOL_H__
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#define __CONTROL_PROTOCOL_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stddef.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <limits.h>
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#include "stdfloat.h"
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#include "firmware_version.h"
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#include "sensor_config_exports.h"
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#include "md5.h"
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#include "status.h"
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#include "utils.h"
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#include "user_config_common.h"
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#define CONTROL_PROTOCOL__MAX_REQUEST_PAYLOAD_SIZE (1024)
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#define CONTROL_PROTOCOL__MAX_READ_MEMORY_DATA_SIZE (1024)
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#define CONTROL_PROTOCOL__MAX_I2C_REGISTER_SIZE (4)
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#define CONTROL_PROTOCOL__MAX_BOARD_NAME_LENGTH (32)
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#define CONTROL_PROTOCOL__MAX_SERIAL_NUMBER_LENGTH (16)
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#define CONTROL_PROTOCOL__MAX_PART_NUMBER_LENGTH (16)
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#define CONTROL_PROTOCOL__MAX_PRODUCT_NAME_LENGTH (42)
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#define CONTROL_PROTOCOL__MAX_CONTEXT_SWITCH_APPLICATIONS (8)
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#define CONTROL_PROTOCOL__MAX_NUMBER_OF_CLUSTERS (8)
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#define CONTROL_PROTOCOL__MAX_CONTROL_LENGTH (1500)
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#define CONTROL_PROTOCOL__MAX_TOTAL_CONTEXTS (32)
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#define CONTROL_PROTOCOL__SOC_ID_LENGTH (32)
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#define CONTROL_PROTOCOL__MAX_CFG_CHANNELS (4)
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#define CONTROL_PROTOCOL__MAX_NETWORKS_PER_NETWORK_GROUP (8)
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/* Tightly coupled with the sizeof PROCESS_MONITOR__detection_results_t
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and HAILO_SOC_PM_VALUES_BYTES_LENGTH */
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#define PM_RESULTS_LENGTH (24)
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/* Tightly coupled to ETHERNET_SERVICE_MAC_ADDRESS_LENGTH */
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#define MAC_ADDR_BYTES_LEN (6)
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#define LOT_ID_BYTES_LEN (8)
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/* Tightly coupled to HAILO_MAX_TEMPERATURE_THROTTLING_LEVELS_NUMBER */
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#define MAX_TEMPERATURE_THROTTLING_LEVELS_NUMBER (4)
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#define CONTROL_PROTOCOL__MAX_NUMBER_OF_POWER_MEASUREMETS (4)
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#define CONTROL_PROTOCOL__DEFAULT_INIT_SAMPLING_PERIOD_US (CONTROL_PROTOCOL__PERIOD_1100US)
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#define CONTROL_PROTOCOL__DEFAULT_INIT_AVERAGING_FACTOR (CONTROL_PROTOCOL__AVERAGE_FACTOR_1)
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#define CONTROL_PROTOCOL__REQUEST_BASE_SIZE (sizeof(CONTROL_PROTOCOL__request_header_t) + sizeof(uint32_t))
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#define CONTROL_PROTOCOL__OPCODE_INVALID 0xFFFFFFFF
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/* If a control accepts a dynamic_batch_size and this value is passed, the
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* dynamic_batch_size will be ignored. The pre-configured batch_size will be used.
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*/
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#define CONTROL_PROTOCOL__IGNORE_DYNAMIC_BATCH_SIZE (0)
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#define CONTROL_PROTOCOL__TRIGGER_SUB_INDEX_SHIFT (0)
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#define CONTROL_PROTOCOL__TRIGGER_SUB_INDEX_BIT_MASK (0x000000FF)
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#define CONTROL_PROTOCOL__TRIGGER_INDEX_SHIFT (16)
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#define CONTROL_PROTOCOL__TRIGGER_INDEX_BIT_MASK (0x00FF0000)
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#define CONTROL_PROTOCOL__TRIGGER_TYPE_SHIFT (28)
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#define CONTROL_PROTOCOL__TRIGGER_TYPE_BIT_MASK (0xF0000000)
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// Tightly coupled with BOARD_CONFIG_supported_features_t struct
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#define CONTROL_PROTOCOL__SUPPORTED_FEATURES_ETHERNET_BIT_OFFSET (0)
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#define CONTROL_PROTOCOL__SUPPORTED_FEATURES_MIPI_BIT_OFFSET (1)
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#define CONTROL_PROTOCOL__SUPPORTED_FEATURES_PCIE_BIT_OFFSET (2)
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#define CONTROL_PROTOCOL__SUPPORTED_FEATURES_CURRENT_MONITORING_BIT_OFFSET (3)
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#define CONTROL_PROTOCOL__SUPPORTED_FEATURES_MDIO_BIT_OFFSET (4)
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#define CONTROL_PROTOCOL_NUM_BIST_CLUSTER_STEPS (8)
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/* Value to represent an operation should be performed on all streams. */
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#define CONTROL_PROTOCOL__ALL_DATAFLOW_MANAGERS (0xFF)
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#define CONTROL_PROTOCOL__WRITE_TRIGGER_SUB_INDEX(val)\
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(((uint32_t)val) << CONTROL_PROTOCOL__TRIGGER_SUB_INDEX_SHIFT)
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#define CONTROL_PROTOCOL__READ_TRIGGER_SUB_INDEX(val)\
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(((uint32_t)(val) & CONTROL_PROTOCOL__TRIGGER_SUB_INDEX_BIT_MASK) >> (CONTROL_PROTOCOL__TRIGGER_SUB_INDEX_SHIFT))
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#define CONTROL_PROTOCOL__WRITE_TRIGGER_INDEX(val)\
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(((uint32_t)val) << CONTROL_PROTOCOL__TRIGGER_INDEX_SHIFT)
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#define CONTROL_PROTOCOL__READ_TRIGGER_INDEX(val)\
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(((uint32_t)(val) & CONTROL_PROTOCOL__TRIGGER_INDEX_BIT_MASK) >> (CONTROL_PROTOCOL__TRIGGER_INDEX_SHIFT))
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#define CONTROL_PROTOCOL__WRITE_TRIGGER_TYPE(val)\
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(((uint32_t)val) << CONTROL_PROTOCOL__TRIGGER_TYPE_SHIFT)
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#define CONTROL_PROTOCOL__READ_TRIGGER_TYPE(val)\
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(((uint32_t)(val) & CONTROL_PROTOCOL__TRIGGER_TYPE_BIT_MASK) >> (CONTROL_PROTOCOL__TRIGGER_TYPE_SHIFT))
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#define CONTROL_PROTOCOL__OPCODES_VARIABLES \
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_IDENTIFY, true, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_WRITE_MEMORY, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_READ_MEMORY, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_CONFIG_STREAM, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_OPEN_STREAM, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_CLOSE_STREAM, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_PHY_OPERATION, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_RESET, true, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_CONFIG_CORE_TOP, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_POWER_MEASUEMENT, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_SET_POWER_MEASUEMENT, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_GET_POWER_MEASUEMENT, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_START_POWER_MEASUEMENT, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_STOP_POWER_MEASUEMENT, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_START_FIRMWARE_UPDATE, true, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_WRITE_FIRMWARE_UPDATE, true, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_VALIDATE_FIRMWARE_UPDATE, true, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_FINISH_FIRMWARE_UPDATE, true, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_EXAMINE_USER_CONFIG, true, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_READ_USER_CONFIG, true, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_ERASE_USER_CONFIG, true, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_WRITE_USER_CONFIG, true, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_I2C_WRITE, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_I2C_READ, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_NN_CORE_LATENCY_MEASUREMENT_CONFIG, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_NN_CORE_LATENCY_MEASUREMENT_READ, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_SENSOR_STORE_CONFIG, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_SENSOR_GET_CONFIG, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_SENSOR_SET_GENERIC_I2C_SLAVE, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_SENSOR_LOAD_AND_START, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_SENSOR_RESET, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_SENSOR_GET_SECTIONS_INFO, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_CONTEXT_SWITCH_SET_MAIN_HEADER, false, CPU_ID_CORE_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_CONTEXT_SWITCH_SET_CONTEXT_INFO, false, CPU_ID_CORE_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_IDLE_TIME_SET_MEASUREMENT, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_IDLE_TIME_GET_MEASUREMENT, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_DOWNLOAD_CONTEXT_ACTION_LIST, false, CPU_ID_CORE_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_CHANGE_CONTEXT_SWITCH_STATUS, false, CPU_ID_CORE_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_APP_WD_ENABLE, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_APP_WD_CONFIG, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_APP_PREVIOUS_SYSTEM_STATE, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_SET_DATAFLOW_INTERRUPT, false, CPU_ID_CORE_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_CORE_IDENTIFY, true, CPU_ID_CORE_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_D2H_EVENT_MANAGER_SET_HOST_INFO, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_D2H_EVENT_MANAGER_SEND_EVENT_HOST_INFO, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_SWITCH_APPLICATION, false, CPU_ID_CORE_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_GET_CHIP_TEMPERATURE, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_READ_BOARD_CONFIG, true, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_WRITE_BOARD_CONFIG, true, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_GET_SOC_ID /* obsolete */, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_ENABLE_DEBUGGING, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_GET_DEVICE_INFORMATION, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_CONFIG_CONTEXT_SWITCH_BREAKPOINT, false, CPU_ID_CORE_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_GET_CONTEXT_SWITCH_BREAKPOINT_STATUS, false, CPU_ID_CORE_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_GET_CONTEXT_SWITCH_MAIN_HEADER, false, CPU_ID_CORE_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_SET_FW_LOGGER, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_WRITE_SECOND_STAGE_TO_INTERNAL_MEMORY, true, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_COPY_SECOND_STAGE_TO_FLASH, true, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_SET_PAUSE_FRAMES, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_CONFIG_CONTEXT_SWITCH_TIMESTAMP, false, CPU_ID_CORE_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_RUN_BIST_TEST, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_SET_CLOCK_FREQ, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_GET_HEALTH_INFORMATION, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_SET_THROTTLING_STATE, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_GET_THROTTLING_STATE, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_SENSOR_SET_I2C_BUS_INDEX, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_SET_OVERCURRENT_STATE, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_GET_OVERCURRENT_STATE, false, CPU_ID_APP_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_CORE_PREVIOUS_SYSTEM_STATE, false, CPU_ID_CORE_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_CORE_WD_ENABLE, false, CPU_ID_CORE_CPU)\
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CONTROL_PROTOCOL__OPCODE_X(HAILO_CONTROL_OPCODE_CORE_WD_CONFIG, false, CPU_ID_CORE_CPU)\
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typedef enum {
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#define CONTROL_PROTOCOL__OPCODE_X(name, is_critical, cpu_id) name,
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CONTROL_PROTOCOL__OPCODES_VARIABLES
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#undef CONTROL_PROTOCOL__OPCODE_X
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/* Must be last!! */
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HAILO_CONTROL_OPCODE_COUNT
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} CONTROL_PROTOCOL__OPCODE_t;
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extern bool g_CONTROL_PROTOCOL__is_critical[HAILO_CONTROL_OPCODE_COUNT];
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typedef enum {
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CONTROL_PROTOCOL__PROTOCOL_VERSION_INITIAL = 0,
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CONTROL_PROTOCOL__PROTOCOL_VERSION_1 = 1,
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CONTROL_PROTOCOL__PROTOCOL_VERSION_2 = 2
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} CONTROL_PROTOCOL__protocol_version_t;
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#define CONTROL_PROTOCOL__PROTOCOL_VERSION (CONTROL_PROTOCOL__PROTOCOL_VERSION_2)
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/*Note: Must be the same as hailo_cpu_id_t in hailort.h */
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typedef enum {
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CPU_ID_APP_CPU,
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CPU_ID_CORE_CPU,
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CPU_ID_UNKNOWN
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} CPU_ID_t;
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extern CPU_ID_t g_CONTROL_PROTOCOL__cpu_id[HAILO_CONTROL_OPCODE_COUNT];
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typedef enum {
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CONTROL_PROTOCOL__ACK_UNSET = 0,
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CONTROL_PROTOCOL__ACK_SET = 1
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} CONTROL_PROTOCOL__ACK_VALUES_t;
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/* Note: Must be the same as hailo_dvm_options_t in hailort.h */
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typedef enum DVM_options_e {
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CONTROL_PROTOCOL__DVM_OPTIONS_VDD_CORE = 0,
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CONTROL_PROTOCOL__DVM_OPTIONS_VDD_IO,
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CONTROL_PROTOCOL__DVM_OPTIONS_MIPI_AVDD,
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CONTROL_PROTOCOL__DVM_OPTIONS_MIPI_AVDD_H,
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CONTROL_PROTOCOL__DVM_OPTIONS_USB_AVDD_IO,
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CONTROL_PROTOCOL__DVM_OPTIONS_VDD_TOP,
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CONTROL_PROTOCOL__DVM_OPTIONS_USB_AVDD_IO_HV,
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CONTROL_PROTOCOL__DVM_OPTIONS_AVDD_H,
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CONTROL_PROTOCOL__DVM_OPTIONS_SDIO_VDD_IO,
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CONTROL_PROTOCOL__DVM_OPTIONS_OVERCURRENT_PROTECTION,
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/* Must be right after the physical DVMS list */
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CONTROL_PROTOCOL__DVM_OPTIONS_COUNT,
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CONTROL_PROTOCOL__DVM_OPTIONS_EVB_TOTAL_POWER = INT_MAX - 1,
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CONTROL_PROTOCOL__DVM_OPTIONS_AUTO = INT_MAX,
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} CONTROL_PROTOCOL__dvm_options_t;
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/* Note: Must be the same as hailo_power_measurement_types_t in hailort.h */
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typedef enum POWER__measurement_types_e {
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CONTROL_PROTOCOL__POWER_MEASUREMENT_TYPES__SHUNT_VOLTAGE = 0,
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CONTROL_PROTOCOL__POWER_MEASUREMENT_TYPES__BUS_VOLTAGE,
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CONTROL_PROTOCOL__POWER_MEASUREMENT_TYPES__POWER,
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CONTROL_PROTOCOL__POWER_MEASUREMENT_TYPES__CURRENT,
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/* Must be Last! */
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CONTROL_PROTOCOL__POWER_MEASUREMENT_TYPES__COUNT,
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CONTROL_PROTOCOL__POWER_MEASUREMENT_TYPES__AUTO = INT_MAX,
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} CONTROL_PROTOCOL__power_measurement_types_t;
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/* Note: Must be the same as hailo_sampling_period_t in hailort.h */
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typedef enum POWER__sampling_period_e {
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CONTROL_PROTOCOL__PERIOD_140US = 0,
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CONTROL_PROTOCOL__PERIOD_204US,
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CONTROL_PROTOCOL__PERIOD_332US,
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CONTROL_PROTOCOL__PERIOD_588US,
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CONTROL_PROTOCOL__PERIOD_1100US,
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CONTROL_PROTOCOL__PERIOD_2116US,
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CONTROL_PROTOCOL__PERIOD_4156US,
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CONTROL_PROTOCOL__PERIOD_8244US,
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} CONTROL_PROTOCOL__sampling_period_t;
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/* Note: Must be the same as hailo_averaging_factor_t in hailort.h */
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typedef enum POWER__averaging_factor_e {
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CONTROL_PROTOCOL__AVERAGE_FACTOR_1 = 0,
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CONTROL_PROTOCOL__AVERAGE_FACTOR_4,
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CONTROL_PROTOCOL__AVERAGE_FACTOR_16,
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CONTROL_PROTOCOL__AVERAGE_FACTOR_64,
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CONTROL_PROTOCOL__AVERAGE_FACTOR_128,
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CONTROL_PROTOCOL__AVERAGE_FACTOR_256,
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CONTROL_PROTOCOL__AVERAGE_FACTOR_512,
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CONTROL_PROTOCOL__AVERAGE_FACTOR_1024,
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} CONTROL_PROTOCOL__averaging_factor_t;
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typedef enum {
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CONTROL_PROTOCOL__PHY_OPERATION_RESET = 0,
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/* Must be last! */
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CONTROL_PROTOCOL__PHY_OPERATION_COUNT
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} CONTROL_PROTOCOL__phy_operation_t;
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/* TODO: add compile time assertion that the protocol is 32-bit aligned */
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/* START OF NETWORK STRUCTURES */
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#pragma pack(push, 1)
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typedef struct {
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uint32_t ack : 1;
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uint32_t reserved : 31;
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} CONTROL_PROTOCOL__flags_struct_t;
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/* Union for easy arithmetic manipulations */
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typedef union {
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CONTROL_PROTOCOL__flags_struct_t bitstruct;
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uint32_t integer;
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} CONTROL_PROTOCOL_flags_t;
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typedef struct {
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uint32_t version;
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CONTROL_PROTOCOL_flags_t flags;
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uint32_t sequence;
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uint32_t opcode;
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} CONTROL_PROTOCOL__common_header_t;
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typedef struct {
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/* Must be first in order to support parsing */
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CONTROL_PROTOCOL__common_header_t common_header;
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} CONTROL_PROTOCOL__request_header_t;
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typedef struct {
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uint32_t major_status;
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uint32_t minor_status;
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} CONTROL_PROTOCOL__status_t;
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typedef struct {
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/* Must be first in order to support parsing */
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CONTROL_PROTOCOL__common_header_t common_header;
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CONTROL_PROTOCOL__status_t status;
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} CONTROL_PROTOCOL__response_header_t;
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#if defined(_MSC_VER)
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// TODO: warning C4200
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#pragma warning(push)
|
||
#pragma warning(disable: 4200)
|
||
#endif
|
||
typedef struct {
|
||
uint32_t length;
|
||
uint8_t data[0];
|
||
} CONTROL_PROTOCOL__parameter_t;
|
||
#if defined(_MSC_VER)
|
||
#pragma warning(pop)
|
||
#endif
|
||
|
||
#if defined(_MSC_VER)
|
||
// TODO: warning C4200
|
||
#pragma warning(push)
|
||
#pragma warning(disable: 4200)
|
||
#endif
|
||
typedef struct {
|
||
uint32_t parameter_count;
|
||
uint8_t parameters[0];
|
||
} CONTROL_PROTOCOL__payload_t;
|
||
#if defined(_MSC_VER)
|
||
#pragma warning(pop)
|
||
#endif
|
||
|
||
typedef struct {
|
||
uint32_t protocol_version_length;
|
||
uint32_t protocol_version;
|
||
uint32_t fw_version_length;
|
||
firmware_version_t fw_version;
|
||
uint32_t logger_version_length;
|
||
uint32_t logger_version;
|
||
uint32_t board_name_length;
|
||
uint8_t board_name[CONTROL_PROTOCOL__MAX_BOARD_NAME_LENGTH];
|
||
uint32_t device_architecture_length;
|
||
uint32_t device_architecture;
|
||
uint32_t serial_number_length;
|
||
uint8_t serial_number[CONTROL_PROTOCOL__MAX_SERIAL_NUMBER_LENGTH];
|
||
uint32_t part_number_length;
|
||
uint8_t part_number[CONTROL_PROTOCOL__MAX_PART_NUMBER_LENGTH];
|
||
uint32_t product_name_length;
|
||
uint8_t product_name[CONTROL_PROTOCOL__MAX_PRODUCT_NAME_LENGTH];
|
||
} CONTROL_PROTOCOL_identify_response_t;
|
||
|
||
typedef struct {
|
||
uint32_t fw_version_length;
|
||
firmware_version_t fw_version;
|
||
} CONTROL_PROTOCOL__core_identify_response_t;
|
||
|
||
typedef enum {
|
||
CONTROL_PROTOCOL__HAILO8_A0 = 0,
|
||
CONTROL_PROTOCOL__HAILO8_B0,
|
||
CONTROL_PROTOCOL__MERCURY_CA,
|
||
CONTROL_PROTOCOL__MERCURY_VPU,
|
||
/* Must be last!! */
|
||
CONTROL_PROTOCOL__DEVICE_ARCHITECTURE_COUNT
|
||
} CONTROL_PROTOCOL__device_architecture_t;
|
||
|
||
typedef enum {
|
||
CONTROL_PROTOCOL__MIPI_DESKEW__FORCE_DISABLE = 0,
|
||
CONTROL_PROTOCOL__MIPI_DESKEW__FORCE_ENABLE,
|
||
CONTROL_PROTOCOL__MIPI_DESKEW__DEFAULT
|
||
} CONTROL_PROTOCOL__mipi_deskew_enable_t;
|
||
|
||
typedef struct {
|
||
uint32_t address_length;
|
||
uint32_t address;
|
||
uint32_t data_count_length;
|
||
uint32_t data_count;
|
||
} CONTROL_PROTOCOL__read_memory_request_t;
|
||
|
||
typedef struct {
|
||
uint32_t data_length;
|
||
uint8_t data[CONTROL_PROTOCOL__MAX_READ_MEMORY_DATA_SIZE];
|
||
} CONTROL_PROTOCOL__read_memory_response_t;
|
||
|
||
#if defined(_MSC_VER)
|
||
// TODO: warning C4200
|
||
#pragma warning(push)
|
||
#pragma warning(disable: 4200)
|
||
#endif
|
||
typedef struct {
|
||
uint32_t address_length;
|
||
uint32_t address;
|
||
uint32_t data_length;
|
||
uint8_t data[0];
|
||
} CONTROL_PROTOCOL__write_memory_request_t;
|
||
|
||
|
||
#if defined(_MSC_VER)
|
||
#pragma warning(pop)
|
||
#endif
|
||
|
||
// Tightly coupled with hailo_fw_logger_interface_t
|
||
typedef enum {
|
||
CONTROL_PROTOCOL__INTERFACE_PCIE = 1 << 0,
|
||
CONTROL_PROTOCOL__INTERFACE_UART = 1 << 1
|
||
} CONTROL_PROTOCOL_interface_t;
|
||
|
||
#define CONTROL_PROTOCOL__FW_MAX_LOGGER_LEVEL (FW_LOGGER_LEVEL_FATAL)
|
||
|
||
#define CONTROL_PROTOCOL__FW_MAX_LOGGER_INTERFACE (CONTROL_PROTOCOL__INTERFACE_PCIE | CONTROL_PROTOCOL__INTERFACE_UART)
|
||
|
||
typedef struct {
|
||
uint32_t level_length;
|
||
uint8_t level; // CONTROL_PROTOCOL_interface_t
|
||
uint32_t logger_interface_bit_mask_length;
|
||
uint8_t logger_interface_bit_mask;
|
||
} CONTROL_PROTOCOL__set_fw_logger_request_t;
|
||
|
||
typedef struct {
|
||
uint32_t should_activate_length;
|
||
bool should_activate;
|
||
} CONTROL_PROTOCOL__set_throttling_state_request_t;
|
||
|
||
typedef struct {
|
||
uint32_t is_active_length;
|
||
bool is_active;
|
||
} CONTROL_PROTOCOL__get_throttling_state_response_t;
|
||
|
||
typedef struct {
|
||
uint32_t should_activate_length;
|
||
bool should_activate;
|
||
} CONTROL_PROTOCOL__set_overcurrent_state_request_t;
|
||
|
||
typedef struct {
|
||
uint32_t is_required_length;
|
||
bool is_required;
|
||
} CONTROL_PROTOCOL__get_overcurrent_state_response_t;
|
||
|
||
typedef struct {
|
||
uint32_t clock_freq_length;
|
||
uint32_t clock_freq;
|
||
} CONTROL_PROTOCOL__set_clock_freq_request_t;
|
||
|
||
typedef struct {
|
||
uint16_t core_bytes_per_buffer;
|
||
uint16_t core_buffers_per_frame;
|
||
uint16_t periph_bytes_per_buffer;
|
||
uint16_t feature_padding_payload;
|
||
uint16_t buffer_padding_payload;
|
||
uint16_t buffer_padding;
|
||
} CONTROL_PROTOCOL__nn_stream_config_t;
|
||
|
||
typedef struct {
|
||
uint16_t host_udp_port;
|
||
uint16_t chip_udp_port;
|
||
uint16_t max_udp_payload_size;
|
||
bool should_send_sync_packets;
|
||
uint32_t buffers_threshold;
|
||
bool use_rtp;
|
||
} CONTROL_PROTOCOL__udp_output_config_params_t;
|
||
|
||
typedef struct {
|
||
uint8_t should_sync;
|
||
uint32_t frames_per_sync;
|
||
uint32_t packets_per_frame;
|
||
uint16_t sync_size;
|
||
} CONTROL_PROTOCOL__udp_input_config_sync_t;
|
||
|
||
typedef struct {
|
||
uint16_t listening_port;
|
||
CONTROL_PROTOCOL__udp_input_config_sync_t sync;
|
||
uint32_t buffers_threshold;
|
||
bool use_rtp;
|
||
} CONTROL_PROTOCOL__udp_input_config_params_t;
|
||
|
||
typedef struct {
|
||
uint8_t data_type;
|
||
uint16_t img_width_pixels; // sensor_out == mipi_in == ISP_in
|
||
uint16_t img_height_pixels; // sensor_out == mipi_in == ISP_in
|
||
uint8_t pixels_per_clock;
|
||
uint8_t number_of_lanes;
|
||
uint8_t clock_selection;
|
||
uint8_t virtual_channel_index;
|
||
uint32_t data_rate;
|
||
} CONTROL_PROTOCOL__mipi_common_config_params_t;
|
||
|
||
typedef struct {
|
||
bool isp_enable;
|
||
uint8_t isp_img_in_order;
|
||
uint8_t isp_img_out_data_type;
|
||
bool isp_crop_enable;
|
||
uint16_t isp_crop_output_width_pixels; // mipi_out == ISP_out == shmifo_in
|
||
uint16_t isp_crop_output_height_pixels; // mipi_out == ISP_out == shmifo_in
|
||
uint16_t isp_crop_output_width_start_offset_pixels;
|
||
uint16_t isp_crop_output_height_start_offset_pixels;
|
||
bool isp_test_pattern_enable;
|
||
bool isp_configuration_bypass;
|
||
bool isp_run_time_ae_enable;
|
||
bool isp_run_time_awb_enable;
|
||
bool isp_run_time_adt_enable;
|
||
bool isp_run_time_af_enable;
|
||
uint16_t isp_run_time_calculations_interval_ms;
|
||
uint8_t isp_light_frequency;
|
||
} CONTROL_PROTOCOL__isp_config_params_t;
|
||
|
||
typedef struct {
|
||
CONTROL_PROTOCOL__mipi_common_config_params_t common_params;
|
||
uint8_t mipi_rx_id;
|
||
CONTROL_PROTOCOL__isp_config_params_t isp_params;
|
||
} CONTROL_PROTOCOL__mipi_input_config_params_t;
|
||
|
||
typedef struct {
|
||
CONTROL_PROTOCOL__mipi_common_config_params_t common_params;
|
||
uint8_t mipi_tx_id;
|
||
uint8_t fifo_threshold_percent;
|
||
uint8_t deskew_enable;
|
||
} CONTROL_PROTOCOL__mipi_output_config_params_t;
|
||
|
||
typedef enum {
|
||
CONTROL_PROTOCOL__PCIE_DATAFLOW_TYPE_CONTINUOUS = 0,
|
||
/* Type 1 (which is CFG flow channel) is not a valid option to be set by the user */
|
||
CONTROL_PROTOCOL__PCIE_DATAFLOW_TYPE_BURST = 2,
|
||
|
||
/* Must be last */
|
||
CONTROL_PROTOCOL__PCIE_DATAFLOW_TYPE_COUNT,
|
||
} CONTROL_PROTOCOL__pcie_dataflow_type_t;
|
||
|
||
typedef struct {
|
||
uint8_t pcie_channel_index;
|
||
uint16_t desc_page_size;
|
||
} CONTROL_PROTOCOL__pcie_output_config_params_t;
|
||
|
||
typedef struct {
|
||
uint8_t pcie_channel_index;
|
||
uint8_t pcie_dataflow_type;
|
||
} CONTROL_PROTOCOL__pcie_input_config_params_t;
|
||
|
||
typedef union {
|
||
CONTROL_PROTOCOL__udp_output_config_params_t udp_output;
|
||
CONTROL_PROTOCOL__udp_input_config_params_t udp_input;
|
||
CONTROL_PROTOCOL__mipi_input_config_params_t mipi_input;
|
||
CONTROL_PROTOCOL__mipi_output_config_params_t mipi_output;
|
||
CONTROL_PROTOCOL__pcie_input_config_params_t pcie_input;
|
||
CONTROL_PROTOCOL__pcie_output_config_params_t pcie_output;
|
||
} CONTROL_PROTOCOL__communication_config_prams_t;
|
||
|
||
// Tightly coupled with hailo_power_mode_t
|
||
typedef enum {
|
||
CONTROL_PROTOCOL__MODE_PERFORMANCE = 0,
|
||
CONTROL_PROTOCOL__MODE_ULTRA_PERFORMANCE = 1,
|
||
|
||
/* Must be last */
|
||
CONTROL_PROTOCOL__POWER_MODE_COUNT
|
||
} CONTROL_PROTOCOL__power_mode_t;
|
||
|
||
typedef struct {
|
||
uint32_t stream_index_length;
|
||
uint8_t stream_index;
|
||
uint32_t is_input_length;
|
||
uint8_t is_input;
|
||
uint32_t communication_type_length;
|
||
uint32_t communication_type;
|
||
uint32_t skip_nn_stream_config_length;
|
||
uint8_t skip_nn_stream_config;
|
||
uint32_t power_mode_length;
|
||
uint8_t power_mode; // CONTROL_PROTOCOL__power_mode_t
|
||
uint32_t nn_stream_config_length;
|
||
CONTROL_PROTOCOL__nn_stream_config_t nn_stream_config;
|
||
// Should be last for size calculations
|
||
uint32_t communication_params_length;
|
||
CONTROL_PROTOCOL__communication_config_prams_t communication_params;
|
||
} CONTROL_PROTOCOL__config_stream_request_t;
|
||
|
||
typedef struct {
|
||
uint32_t dataflow_manager_id_length;
|
||
uint8_t dataflow_manager_id;
|
||
uint32_t is_input_length;
|
||
uint8_t is_input;
|
||
} CONTROL_PROTOCOL__open_stream_request_t;
|
||
|
||
typedef struct {
|
||
uint32_t dataflow_manager_id_length;
|
||
uint8_t dataflow_manager_id;
|
||
uint32_t is_input_length;
|
||
uint8_t is_input;
|
||
} CONTROL_PROTOCOL__close_stream_request_t;
|
||
|
||
typedef struct {
|
||
uint32_t operation_type_length;
|
||
uint32_t operation_type;
|
||
} CONTROL_PROTOCOL__phy_operation_request_t;
|
||
|
||
typedef struct {
|
||
uint32_t rx_pause_frames_enable_length;
|
||
uint8_t rx_pause_frames_enable;
|
||
} CONTROL_PROTOCOL__set_pause_frames_t;
|
||
|
||
typedef struct {
|
||
uint32_t reset_type_length;
|
||
uint32_t reset_type;
|
||
} CONTROL_PROTOCOL__reset_request_t;
|
||
|
||
typedef enum {
|
||
CONTROL_PROTOCOL__CONFIG_CORE_TOP_TYPE_AHB_TO_AXI = 0,
|
||
|
||
/* Must be last! */
|
||
CONTROL_PROTOCOL__CONFIG_CORE_TOP_OPCODE_COUNT
|
||
} CONTROL_PROTOCOL__config_core_top_type_t;
|
||
|
||
typedef struct {
|
||
uint8_t enable_use_64bit_data_only;
|
||
} CONTROL_PROTOCOL__config_ahb_to_axi_params_t;
|
||
|
||
typedef union {
|
||
CONTROL_PROTOCOL__config_ahb_to_axi_params_t ahb_to_axi;
|
||
} CONTROL_PROTOCOL__config_core_top_params_t;
|
||
|
||
typedef struct {
|
||
uint32_t config_type_length;
|
||
uint32_t config_type;
|
||
uint32_t config_params_length;
|
||
CONTROL_PROTOCOL__config_core_top_params_t config_params;
|
||
} CONTROL_PROTOCOL__config_core_top_request_t;
|
||
|
||
typedef struct {
|
||
uint32_t dvm_length;
|
||
uint32_t dvm;
|
||
uint32_t measurement_type_length;
|
||
uint32_t measurement_type;
|
||
} CONTROL_PROTOCOL__power_measurement_request_t;
|
||
|
||
typedef struct {
|
||
uint32_t power_measurement_length;
|
||
float32_t power_measurement;
|
||
uint32_t dvm_length;
|
||
uint32_t dvm;
|
||
uint32_t measurement_type_length;
|
||
uint32_t measurement_type;
|
||
} CONTROL_PROTOCOL__power_measurement_response_t;
|
||
|
||
typedef struct {
|
||
uint32_t index_length;
|
||
uint32_t index;
|
||
uint32_t dvm_length;
|
||
uint32_t dvm;
|
||
uint32_t measurement_type_length;
|
||
uint32_t measurement_type;
|
||
} CONTROL_PROTOCOL__set_power_measurement_request_t;
|
||
|
||
typedef struct {
|
||
uint32_t dvm_length;
|
||
uint32_t dvm;
|
||
uint32_t measurement_type_length;
|
||
uint32_t measurement_type;
|
||
} CONTROL_PROTOCOL__set_power_measurement_response_t;
|
||
|
||
typedef struct {
|
||
uint32_t index_length;
|
||
uint32_t index;
|
||
uint32_t should_clear_length;
|
||
uint8_t should_clear;
|
||
} CONTROL_PROTOCOL__get_power_measurement_request_t;
|
||
|
||
typedef struct {
|
||
uint32_t total_number_of_samples_length;
|
||
uint32_t total_number_of_samples;
|
||
uint32_t min_value_length;
|
||
float32_t min_value;
|
||
uint32_t max_value_length;
|
||
float32_t max_value;
|
||
uint32_t average_value_length;
|
||
float32_t average_value;
|
||
uint32_t average_time_value_milliseconds_length;
|
||
float32_t average_time_value_milliseconds;
|
||
} CONTROL_PROTOCOL__get_power_measurement_response_t;
|
||
|
||
typedef struct {
|
||
uint32_t delay_milliseconds_length;
|
||
uint32_t delay_milliseconds;
|
||
uint32_t averaging_factor_length;
|
||
uint16_t averaging_factor;
|
||
uint32_t sampling_period_length;
|
||
uint16_t sampling_period;
|
||
} CONTROL_PROTOCOL__start_power_measurement_request_t;
|
||
|
||
|
||
typedef struct {
|
||
uint32_t endianness_length;
|
||
uint8_t endianness;
|
||
uint32_t slave_address_length;
|
||
uint16_t slave_address;
|
||
uint32_t register_address_size_length;
|
||
uint8_t register_address_size;
|
||
uint32_t bus_index_length;
|
||
uint8_t bus_index;
|
||
uint32_t should_hold_bus_length;
|
||
uint8_t should_hold_bus;
|
||
} CONTROL_PROTOCOL__i2c_slave_config_t;
|
||
|
||
|
||
#if defined(_MSC_VER)
|
||
// TODO: warning C4200
|
||
#pragma warning(push)
|
||
#pragma warning(disable: 4200)
|
||
#endif
|
||
typedef struct {
|
||
CONTROL_PROTOCOL__i2c_slave_config_t slave_config;
|
||
uint32_t register_address_size;
|
||
uint32_t register_address;
|
||
uint32_t data_length;
|
||
uint8_t data[0];
|
||
} CONTROL_PROTOCOL__i2c_write_request_t;
|
||
#if defined(_MSC_VER)
|
||
#pragma warning(pop)
|
||
#endif
|
||
|
||
typedef struct {
|
||
CONTROL_PROTOCOL__i2c_slave_config_t slave_config;
|
||
uint32_t register_address_size;
|
||
uint32_t register_address;
|
||
uint32_t data_length_length;
|
||
uint32_t data_length;
|
||
} CONTROL_PROTOCOL__i2c_read_request_t;
|
||
|
||
typedef struct {
|
||
uint32_t data_length;
|
||
uint8_t data[CONTROL_PROTOCOL__MAX_I2C_REGISTER_SIZE];
|
||
} CONTROL_PROTOCOL__i2c_read_response_t;
|
||
|
||
#if defined(_MSC_VER)
|
||
// TODO: warning C4200
|
||
#pragma warning(push)
|
||
#pragma warning(disable: 4200)
|
||
#endif
|
||
typedef struct {
|
||
uint32_t offset_length;
|
||
uint32_t offset;
|
||
uint32_t data_length;
|
||
uint8_t data[0];
|
||
} CONTROL_PROTOCOL__write_firmware_update_request_t;
|
||
#if defined(_MSC_VER)
|
||
#pragma warning(pop)
|
||
#endif
|
||
|
||
typedef struct {
|
||
uint32_t expected_md5_length;
|
||
MD5_SUM_t expected_md5;
|
||
uint32_t firmware_size_length;
|
||
uint32_t firmware_size;
|
||
} CONTROL_PROTOCOL__validate_firmware_update_request_t;
|
||
|
||
typedef CONTROL_PROTOCOL__write_firmware_update_request_t CONTROL_PROTOCOL__write_second_stage_to_internal_memory_request_t;
|
||
typedef struct {
|
||
uint32_t expected_md5_length;
|
||
MD5_SUM_t expected_md5;
|
||
uint32_t second_stage_size_length;
|
||
uint32_t second_stage_size;
|
||
} CONTROL_PROTOCOL__copy_second_stage_to_flash_request_t;
|
||
|
||
typedef struct {
|
||
uint32_t version_length;
|
||
uint32_t version;
|
||
uint32_t entry_count_length;
|
||
uint32_t entry_count;
|
||
uint32_t total_size_length;
|
||
uint32_t total_size;
|
||
} CONTROL_PROTOCOL__examine_user_config_response_t;
|
||
|
||
typedef struct {
|
||
uint32_t latency_measurement_en_length;
|
||
uint8_t latency_measurement_en;
|
||
uint32_t inbound_start_buffer_number_length;
|
||
uint32_t inbound_start_buffer_number;
|
||
uint32_t outbound_stop_buffer_number_length;
|
||
uint32_t outbound_stop_buffer_number;
|
||
uint32_t inbound_stream_index_length;
|
||
uint32_t inbound_stream_index;
|
||
uint32_t outbound_stream_index_length;
|
||
uint32_t outbound_stream_index;
|
||
} CONTROL_PROTOCOL__latency_config_request_t;
|
||
|
||
|
||
#if defined(_MSC_VER)
|
||
// TODO: warning C4200
|
||
#pragma warning(push)
|
||
#pragma warning(disable: 4200)
|
||
#endif
|
||
typedef struct {
|
||
uint32_t section_index_length;
|
||
uint32_t section_index;
|
||
uint32_t is_first_length;
|
||
uint32_t is_first;
|
||
uint32_t start_offset_length;
|
||
uint32_t start_offset;
|
||
uint32_t reset_data_size_length;
|
||
uint32_t reset_data_size;
|
||
uint32_t sensor_type_length;
|
||
uint32_t sensor_type;
|
||
uint32_t total_data_size_length;
|
||
uint32_t total_data_size;
|
||
uint32_t config_height_length;
|
||
uint16_t config_height;
|
||
uint32_t config_width_length;
|
||
uint16_t config_width;
|
||
uint32_t config_fps_length;
|
||
uint16_t config_fps;
|
||
uint32_t config_name_length;
|
||
uint8_t config_name[MAX_CONFIG_NAME_LEN];
|
||
uint32_t data_length;
|
||
uint8_t data[0];
|
||
} CONTROL_PROTOCOL__sensor_store_config_request_t;
|
||
#if defined(_MSC_VER)
|
||
#pragma warning(pop)
|
||
#endif
|
||
|
||
typedef struct {
|
||
uint32_t section_index_length;
|
||
uint32_t section_index;
|
||
uint32_t offset_length;
|
||
uint32_t offset;
|
||
uint32_t data_size_length;
|
||
uint32_t data_size;
|
||
} CONTROL_PROTOCOL__sensor_get_config_request_t;
|
||
|
||
typedef struct {
|
||
uint32_t sensor_type_length;
|
||
uint32_t sensor_type;
|
||
uint32_t i2c_bus_index_length;
|
||
uint32_t i2c_bus_index;
|
||
} CONTROL_PROTOCOL__sensor_set_i2c_bus_index_t;
|
||
|
||
typedef struct {
|
||
uint32_t section_index_length;
|
||
uint32_t section_index;
|
||
} CONTROL_PROTOCOL__sensor_load_config_request_t;
|
||
|
||
typedef struct {
|
||
uint32_t slave_address_length;
|
||
uint16_t slave_address;
|
||
uint32_t register_address_size_length;
|
||
uint8_t register_address_size;
|
||
uint32_t bus_index_length;
|
||
uint8_t bus_index;
|
||
uint32_t should_hold_bus_length;
|
||
uint8_t should_hold_bus;
|
||
uint32_t endianness_length;
|
||
uint8_t endianness;
|
||
}CONTROL_PROTOCOL__sensor_set_generic_i2c_slave_request_t;
|
||
|
||
typedef struct {
|
||
uint32_t section_index_length;
|
||
uint32_t section_index;
|
||
} CONTROL_PROTOCOL__sensor_reset_request_t;
|
||
|
||
typedef struct {
|
||
uint32_t data_length;
|
||
uint8_t data[CONTROL_PROTOCOL__MAX_READ_MEMORY_DATA_SIZE];
|
||
} CONTROL_PROTOCOL__sensor_get_config_response_t;
|
||
|
||
typedef struct {
|
||
uint32_t data_length;
|
||
uint8_t data[CONTROL_PROTOCOL__MAX_READ_MEMORY_DATA_SIZE];
|
||
} CONTROL_PROTOCOL__sensor_get_sections_info_response_t;
|
||
|
||
typedef struct {
|
||
uint32_t inbound_to_outbound_latency_nsec_length;
|
||
uint32_t inbound_to_outbound_latency_nsec;
|
||
} CONTROL_PROTOCOL__latency_read_response_t;
|
||
|
||
typedef enum {
|
||
CONTROL_PROTOCOL__CONTEXT_SWITCH_VER_V1_0_0 = 0x010000,
|
||
} CONTROL_PROTOCOL__CONTEXT_SWITCH_VERSION_t;
|
||
|
||
typedef struct {
|
||
bool is_abbale_supported;
|
||
} CONTROL_PROTOCOL__VALIDATION_FEATURE_LIST_t;
|
||
|
||
typedef struct {
|
||
bool preliminary_run_asap;
|
||
} CONTROL_PROTOCOL__INFER_FEATURE_LIST_t;
|
||
|
||
typedef struct {
|
||
uint8_t dynamic_contexts_count;
|
||
uint32_t host_boundary_channels_bitmap;
|
||
uint8_t cfg_channel_numbers[CONTROL_PROTOCOL__MAX_CFG_CHANNELS];
|
||
uint8_t power_mode; // CONTROL_PROTOCOL__power_mode_t
|
||
CONTROL_PROTOCOL__INFER_FEATURE_LIST_t infer_features;
|
||
uint8_t networks_count;
|
||
uint16_t batch_size[CONTROL_PROTOCOL__MAX_NETWORKS_PER_NETWORK_GROUP];
|
||
} CONTROL_PROTOCOL__application_header_t;
|
||
|
||
typedef struct {
|
||
uint32_t context_switch_version_length;
|
||
uint32_t context_switch_version;
|
||
uint32_t validation_features_length;
|
||
CONTROL_PROTOCOL__VALIDATION_FEATURE_LIST_t validation_features;
|
||
uint32_t application_count_length;
|
||
uint8_t application_count;
|
||
uint32_t application_header_length;
|
||
CONTROL_PROTOCOL__application_header_t application_header[CONTROL_PROTOCOL__MAX_CONTEXT_SWITCH_APPLICATIONS];
|
||
} CONTROL_PROTOCOL__context_switch_set_main_header_request_t;
|
||
|
||
typedef enum {
|
||
CONTROL_PROTOCOL__WATCHDOG_MODE_HW_SW = 0,
|
||
CONTROL_PROTOCOL__WATCHDOG_MODE_HW_ONLY,
|
||
|
||
/* must be last*/
|
||
CONTROL_PROTOCOL__WATCHDOG_NUM_MODES,
|
||
} CONTROL_PROTOCOL__WATCHDOG_MODE_t;
|
||
|
||
typedef struct {
|
||
CONTROL_PROTOCOL__CONTEXT_SWITCH_VERSION_t context_switch_version;
|
||
CONTROL_PROTOCOL__VALIDATION_FEATURE_LIST_t validation_features;
|
||
uint8_t application_count;
|
||
CONTROL_PROTOCOL__application_header_t application_header[CONTROL_PROTOCOL__MAX_CONTEXT_SWITCH_APPLICATIONS];
|
||
} CONTROL_PROTOCOL__context_switch_main_header_t;
|
||
|
||
typedef struct {
|
||
uint32_t should_enable_length;
|
||
uint8_t should_enable;
|
||
} CONTROL_PROTOCOL__wd_enable_request_t;
|
||
|
||
typedef struct {
|
||
uint32_t wd_cycles_length;
|
||
uint32_t wd_cycles;
|
||
uint32_t wd_mode_length;
|
||
uint8_t wd_mode;
|
||
} CONTROL_PROTOCOL__wd_config_request_t;
|
||
|
||
/* TODO: Define bit struct (SDK-14509). */
|
||
typedef uint32_t CONTROL_PROTOCOL__system_state_t;
|
||
typedef struct {
|
||
uint32_t system_state_length;
|
||
CONTROL_PROTOCOL__system_state_t system_state;
|
||
} CONTROL_PROTOCOL__previous_system_state_response_t;
|
||
|
||
typedef struct {
|
||
float32_t ts0_temperature;
|
||
float32_t ts1_temperature;
|
||
uint16_t sample_count;
|
||
} CONTROL_PROTOCOL__temperature_info_t;
|
||
|
||
typedef struct {
|
||
uint32_t info_length;
|
||
CONTROL_PROTOCOL__temperature_info_t info;
|
||
} CONTROL_PROTOCOL__get_chip_temperature_response_t;
|
||
|
||
typedef enum {
|
||
CONTROL_PROTOCOL__CONTEXT_SWITCH_TRIGGER_TYPE_NONE = 0,
|
||
CONTROL_PROTOCOL__CONTEXT_SWITCH_TRIGGER_TYPE_LCU,
|
||
CONTROL_PROTOCOL__CONTEXT_SWITCH_TRIGGER_TYPE_INPUT_STREAM,
|
||
CONTROL_PROTOCOL__CONTEXT_SWITCH_TRIGGER_TYPE_OUTPUT_STREAM,
|
||
CONTROL_PROTOCOL__CONTEXT_SWITCH_TRIGGER_TYPE_NMS_IDLE,
|
||
CONTROL_PROTOCOL__CONTEXT_SWITCH_TRIGGER_TYPE_DMA_IDLE,
|
||
|
||
/* must be last*/
|
||
CONTROL_PROTOCOL__CONTEXT_SWITCH_TRIGGER_TYPE_COUNT,
|
||
} CONTROL_PROTOCOL__CONTEXT_SWITCH_TRIGGER_TYPE_t;
|
||
|
||
typedef enum {
|
||
/* this enum starts from 128 for each debug while reading memory buffer */
|
||
CONTROL_PROTOCOL__CONTEXT_SWITCH_ACTION_START_INDEX = 128,
|
||
CONTROL_PROTOCOL__CONTEXT_SWITCH_ACTION_READ_VDMA = CONTROL_PROTOCOL__CONTEXT_SWITCH_ACTION_START_INDEX,
|
||
CONTROL_PROTOCOL__CONTEXT_SWITCH_ACTION_TRIGGER_SEQUENCER,
|
||
CONTROL_PROTOCOL__CONTEXT_SWITCH_ACTION_WAIT_FOR_SEQUENCER_DONE,
|
||
CONTROL_PROTOCOL__CONTEXT_SWITCH_ACTION_TRIGGER_NEW_DATA_FROM_DATA_INPUT,
|
||
CONTROL_PROTOCOL__CONTEXT_SWITCH_ACTION_ENABLE_LCU_NON_DEFAULT,
|
||
CONTROL_PROTOCOL__CONTEXT_SWITCH_ACTION_DISABLE_LCU,
|
||
CONTROL_PROTOCOL__CONTEXT_SWITCH_ACTION_WAIT_FOR_MODULE_CONFIG_DONE,
|
||
CONTROL_PROTOCOL__CONTEXT_SWITCH_ACTION_ADD_DDR_PAIR_INFO,
|
||
CONTROL_PROTOCOL__CONTEXT_SWITCH_ACTION_ADD_DDR_BUFFERING_START,
|
||
CONTROL_PROTOCOL__CONTEXT_SWITCH_ACTION_ENABLE_LCU_DEFAULT,
|
||
CONTROL_PROTOCOL__CONTEXT_SWITCH_ACTION_ADD_REPEATED,
|
||
CONTROL_PROTOCOL__CONTEXT_SWITCH_ACTION_FETCH_CCW_BURSTS,
|
||
CONTROL_PROTOCOL__CONTEXT_SWITCH_ACTION_BURST_CREDITS_TASK_START,
|
||
|
||
/* must be last*/
|
||
CONTROL_PROTOCOL__CONTEXT_SWITCH_ACTION_COUNT,
|
||
} CONTROL_PROTOCOL__CONTEXT_SWITCH_ACTION_TYPE_t;
|
||
|
||
typedef uint8_t CONTROL_PROTOCOL__TRIGGER_TYPE_t;
|
||
|
||
typedef struct {
|
||
/* Empty struct - place holder */
|
||
uint8_t reserved;
|
||
} CONTROL_PROTOCOL__TRIGGER_NONE_t;
|
||
|
||
typedef struct {
|
||
uint8_t cluster_index;
|
||
uint8_t lcu_index;
|
||
} CONTROL_PROTOCOL__TRIGGER_LCU_t;
|
||
|
||
typedef struct {
|
||
uint8_t stream_index;
|
||
} CONTROL_PROTOCOL__TRIGGER_INPUT_STREAM_t;
|
||
|
||
typedef struct {
|
||
uint8_t stream_index;
|
||
} CONTROL_PROTOCOL__TRIGGER_OUTPUT_STREAM_t;
|
||
|
||
typedef struct {
|
||
uint8_t aggregator_index;
|
||
uint8_t pred_cluster_ob_index;
|
||
uint8_t pred_cluster_ob_cluster_index;
|
||
uint8_t pred_cluster_ob_interface;
|
||
uint8_t succ_prepost_ob_index;
|
||
uint8_t succ_prepost_ob_interface;
|
||
} CONTROL_PROTOCOL__TRIGGER_NMS_IDLE_t;
|
||
|
||
typedef struct {
|
||
uint8_t stream_index;
|
||
} CONTROL_PROTOCOL__TRIGGER_DMA_IDLE_t;
|
||
|
||
typedef union {
|
||
CONTROL_PROTOCOL__TRIGGER_NONE_t none_trigger;
|
||
CONTROL_PROTOCOL__TRIGGER_LCU_t lcu_trigger;
|
||
CONTROL_PROTOCOL__TRIGGER_INPUT_STREAM_t input_stream_trigger;
|
||
CONTROL_PROTOCOL__TRIGGER_OUTPUT_STREAM_t output_stream_trigger;
|
||
CONTROL_PROTOCOL__TRIGGER_NMS_IDLE_t nms_idle_trigger;
|
||
CONTROL_PROTOCOL__TRIGGER_DMA_IDLE_t dma_idle_trigger;
|
||
} CONTROL_PROTOCOL__trigger_parameters_t;
|
||
|
||
typedef struct {
|
||
CONTROL_PROTOCOL__TRIGGER_TYPE_t type;
|
||
CONTROL_PROTOCOL__trigger_parameters_t params;
|
||
} CONTROL_PROTOCOL__TRIGGER_t;
|
||
|
||
typedef uint8_t CONTROL_PROTOCOL__shmifo_to_pcie_channel_mapping_t;
|
||
|
||
typedef enum {
|
||
CONTROL_PROTOCOL__EDGE_CONNECTION_TYPE_NETWORK_BOUNDARY_INPUT,
|
||
CONTROL_PROTOCOL__EDGE_CONNECTION_TYPE_NETWORK_BOUNDARY_OUTPUT,
|
||
CONTROL_PROTOCOL__EDGE_CONNECTION_TYPE_INTERMEDIATE_BUFFER_INPUT,
|
||
CONTROL_PROTOCOL__EDGE_CONNECTION_TYPE_INTERMEDIATE_BUFFER_OUTPUT,
|
||
CONTROL_PROTOCOL__EDGE_CONNECTION_TYPE_DDR_BUFFER_INPUT,
|
||
CONTROL_PROTOCOL__EDGE_CONNECTION_TYPE_DDR_BUFFER_OUTPUT,
|
||
|
||
/* must be last */
|
||
CONTROL_PROTOCOL__EDGE_CONNECTION_TYPE_COUNT
|
||
} CONTROL_PROTOCOL__EDGE_CONNECTION_TYPE_t;
|
||
|
||
typedef enum {
|
||
CONTROL_PROTOCOL__HOST_BUFFER_TYPE_EXTERNAL_DESC = 0,
|
||
CONTROL_PROTOCOL__HOST_BUFFER_TYPE_CCB,
|
||
|
||
// The buffer uses external descriptors that is host managed - the firmware don't need to config this buffer
|
||
CONTROL_PROTOCOL__HOST_BUFFER_TYPE_HOST_MANAGED_EXTERNAL_DESC,
|
||
|
||
/* must be last*/
|
||
CONTROL_PROTOCOL__HOST_BUFFER_TYPE_COUNT
|
||
} CONTROL_PROTOCOL__HOST_BUFFER_TYPE_t;
|
||
|
||
typedef struct {
|
||
uint8_t buffer_type; // CONTROL_PROTOCOL__HOST_BUFFER_TYPE_t
|
||
uint64_t dma_address;
|
||
uint16_t desc_page_size;
|
||
uint32_t total_desc_count;
|
||
uint32_t bytes_in_pattern;
|
||
} CONTROL_PROTOCOL__host_buffer_info_t;
|
||
|
||
typedef struct {
|
||
uint8_t communication_type;
|
||
uint8_t edge_connection_type;
|
||
} CONTROL_PROTOCOL__edge_layer_header_t;
|
||
|
||
typedef struct {
|
||
uint8_t stream_index;
|
||
uint8_t vdma_channel_index;
|
||
uint8_t network_index;
|
||
CONTROL_PROTOCOL__nn_stream_config_t nn_stream_config;
|
||
} CONTROL_PROTOCOL__edge_layer_common_info_t;
|
||
|
||
typedef struct {
|
||
uint64_t host_descriptors_base_address;
|
||
uint8_t desc_list_depth;
|
||
} CONTROL_PROTOCOL__host_desc_address_info_t;
|
||
|
||
typedef struct {
|
||
CONTROL_PROTOCOL__edge_layer_common_info_t common_info;
|
||
uint32_t frame_credits_in_bytes;
|
||
uint16_t desc_page_size;
|
||
} CONTROL_PROTOCOL__network_boundary_output_t;
|
||
|
||
typedef struct {
|
||
CONTROL_PROTOCOL__edge_layer_common_info_t common_info;
|
||
CONTROL_PROTOCOL__host_buffer_info_t host_buffer_info;
|
||
} CONTROL_PROTOCOL__inter_context_output_t;
|
||
|
||
typedef struct {
|
||
CONTROL_PROTOCOL__edge_layer_common_info_t common_info;
|
||
uint32_t frame_credits_in_bytes;
|
||
CONTROL_PROTOCOL__host_desc_address_info_t host_desc_address_info;
|
||
uint16_t desc_page_size;
|
||
uint32_t buffered_rows_count;
|
||
} CONTROL_PROTOCOL__ddr_buffer_output_t;
|
||
|
||
|
||
typedef struct {
|
||
CONTROL_PROTOCOL__edge_layer_common_info_t common_info;
|
||
} CONTROL_PROTOCOL__eth_network_boundary_output_t;
|
||
|
||
typedef struct {
|
||
CONTROL_PROTOCOL__edge_layer_common_info_t common_info;
|
||
uint16_t desc_page_size;
|
||
uint32_t initial_credit_size;
|
||
} CONTROL_PROTOCOL__network_boundary_input_t;
|
||
|
||
typedef struct {
|
||
CONTROL_PROTOCOL__edge_layer_common_info_t common_info;
|
||
CONTROL_PROTOCOL__host_buffer_info_t host_buffer_info;
|
||
uint32_t initial_credit_size;
|
||
} CONTROL_PROTOCOL__inter_context_input_t;
|
||
|
||
typedef struct {
|
||
CONTROL_PROTOCOL__edge_layer_common_info_t common_info;
|
||
CONTROL_PROTOCOL__host_desc_address_info_t host_desc_address_info;
|
||
uint32_t initial_credit_size;
|
||
} CONTROL_PROTOCOL__ddr_buffer_input_t;
|
||
|
||
typedef struct {
|
||
CONTROL_PROTOCOL__edge_layer_common_info_t common_info;
|
||
} CONTROL_PROTOCOL__eth_network_boundary_input_t;
|
||
|
||
typedef struct {
|
||
uint8_t should_use_stream_remap;
|
||
} CONTROL_PROTOCOL__stream_remap_data_t;
|
||
|
||
#if defined(_MSC_VER)
|
||
// TODO: warning C4200
|
||
#pragma warning(push)
|
||
#pragma warning(disable: 4200)
|
||
#endif
|
||
typedef struct {
|
||
uint32_t is_first_control_per_context_length;
|
||
uint8_t is_first_control_per_context;
|
||
uint32_t is_last_control_per_context_length;
|
||
uint8_t is_last_control_per_context;
|
||
uint32_t cfg_channels_count_length;
|
||
uint8_t cfg_channels_count;
|
||
uint32_t config_buffer_infos_length;
|
||
CONTROL_PROTOCOL__host_buffer_info_t config_buffer_infos[CONTROL_PROTOCOL__MAX_CFG_CHANNELS];
|
||
uint32_t context_stream_remap_data_length;
|
||
CONTROL_PROTOCOL__stream_remap_data_t context_stream_remap_data;
|
||
uint32_t number_of_edge_layers_length;
|
||
uint8_t number_of_edge_layers;
|
||
uint32_t number_of_trigger_groups_length;
|
||
uint8_t number_of_trigger_groups;
|
||
uint32_t context_network_data_length;
|
||
uint8_t context_network_data[0];
|
||
} CONTROL_PROTOCOL__context_switch_set_context_info_request_t;
|
||
#if defined(_MSC_VER)
|
||
#pragma warning(pop)
|
||
#endif
|
||
|
||
typedef uint8_t CONTROL_PROTOCOL__ACTION_TYPE_t;
|
||
|
||
/* Each CONTROL_PROTOCOL__*_ACTION_t must start with a CONTROL_PROTOCOL__ACTION_HEADER_t */
|
||
typedef struct {
|
||
/* Must be first */
|
||
CONTROL_PROTOCOL__ACTION_TYPE_t action_type;
|
||
bool is_repeated;
|
||
} CONTROL_PROTOCOL__ACTION_HEADER_t;
|
||
|
||
/**
|
||
* Repeated actions are sent in the following manner via the control protocol:
|
||
* 1) CONTROL_PROTOCOL__REPEATED_ACTION_t with:
|
||
* a) 'action_type' = CONTROL_PROTOCOL__CONTEXT_SWITCH_ACTION_ADD_REPEATED
|
||
* b) 'is_repeated' = false
|
||
* 2) 'count' sub-actions whose type matches the 'sub_action_type' defined by (1).
|
||
* The sub-actions will be consecutive, and will all be marked as 'is_repeated' = true in thier headers.
|
||
* The sub-actions may be in different slices, if there is a 'CONTROL_PROTOCOL__CONTEXT_SWITCH_TRIGGER_TYPE_NONE' between them.
|
||
*
|
||
* E.g. - 3 repeated 'CONTROL_PROTOCOL__CONTEXT_SWITCH_ACTION_ENABLE_LCU_DEFAULT's:
|
||
* |--------------------------------------------------------------------------------------------------|
|
||
* | time | data |
|
||
* |--------------------------------------------------------------------------------------------------|
|
||
* | ... | |
|
||
* | | | CONTROL_PROTOCOL__REPEATED_ACTION_t { |
|
||
* | | | .header = { CONTROL_PROTOCOL__CONTEXT_SWITCH_ACTION_ADD_REPEATED, false}; |
|
||
* | | | .sub_action_type = CONTROL_PROTOCOL__CONTEXT_SWITCH_ACTION_ENABLE_LCU_DEFAULT; |
|
||
* | | | .num_actions = 3; |
|
||
* | | | } |
|
||
* | | | CONTROL_PROTOCOL__ENABLE_LCU_DEFAULT_ACTION_t { |
|
||
* | | | .header = { CONTROL_PROTOCOL__CONTEXT_SWITCH_ACTION_ENABLE_LCU_DEFAULT, true }; |
|
||
* | | | .cluster_index = <some_cluster_index>; |
|
||
* | | | .lcu_index = <some_lcu_index>; |
|
||
* | | | .network_index = <some_network_index>; |
|
||
* | | | } |
|
||
* | | | CONTROL_PROTOCOL__ENABLE_LCU_DEFAULT_ACTION_t { |
|
||
* | | | .header = { CONTROL_PROTOCOL__CONTEXT_SWITCH_ACTION_ENABLE_LCU_DEFAULT, true }; |
|
||
* | | | .cluster_index = <some_cluster_index>; |
|
||
* | | | .lcu_index = <some_lcu_index>; |
|
||
* | | | .network_index = <some_network_index>; |
|
||
* | | | } |
|
||
* | | | CONTROL_PROTOCOL__ENABLE_LCU_DEFAULT_ACTION_t { |
|
||
* | | | .header = { CONTROL_PROTOCOL__CONTEXT_SWITCH_ACTION_ENABLE_LCU_DEFAULT, true }; |
|
||
* | | | .cluster_index = <some_cluster_index>; |
|
||
* | | | .lcu_index = <some_lcu_index>; |
|
||
* | | | .network_index = <some_network_index>; |
|
||
* | V | } |
|
||
* | ... | (Next action control) |
|
||
* |--------------------------------------------------------------------------------------------------|
|
||
* See also: "CONTEXT_SWITCH_DEFS__repeated_action_header_t" in "context_switch_defs.h"
|
||
*/
|
||
typedef struct {
|
||
/* Must be first */
|
||
CONTROL_PROTOCOL__ACTION_HEADER_t header;
|
||
CONTROL_PROTOCOL__ACTION_TYPE_t sub_action_type;
|
||
uint8_t num_actions;
|
||
} CONTROL_PROTOCOL__REPEATED_ACTION_t;
|
||
|
||
typedef struct {
|
||
/* Must be first */
|
||
CONTROL_PROTOCOL__ACTION_HEADER_t header;
|
||
uint16_t descriptors_count;
|
||
uint8_t cfg_channel_handle;
|
||
} CONTROL_PROTOCOL__READ_VDMA_ACTION_t;
|
||
|
||
typedef struct {
|
||
/* Must be first */
|
||
CONTROL_PROTOCOL__ACTION_HEADER_t header;
|
||
uint16_t ccw_bursts;
|
||
uint8_t cfg_channel_handle;
|
||
} CONTROL_PROTOCOL__FETCH_CCW_BURSTS_ACTION_t;
|
||
|
||
typedef struct {
|
||
uint8_t initial_l3_cut;
|
||
uint16_t initial_l3_offset;
|
||
uint32_t active_apu;
|
||
uint32_t active_ia;
|
||
uint64_t active_sc;
|
||
uint64_t active_l2;
|
||
uint64_t l2_offset_0;
|
||
uint64_t l2_offset_1;
|
||
} CONTORL_PROTOCOL__sequencer_config_t;
|
||
|
||
typedef struct {
|
||
/* Must be first */
|
||
CONTROL_PROTOCOL__ACTION_HEADER_t header;
|
||
uint8_t cluster_index;
|
||
CONTORL_PROTOCOL__sequencer_config_t sequencer_config;
|
||
} CONTROL_PROTOCOL__TRIGGER_SEQUENCER_ACTION_t;
|
||
|
||
typedef struct {
|
||
/* Must be first */
|
||
CONTROL_PROTOCOL__ACTION_HEADER_t header;
|
||
uint8_t sequencer_index;
|
||
} CONTROL_PROTOCOL__WAIT_FOR_SEQUENCER_ACTION_t;
|
||
|
||
typedef struct {
|
||
/* Must be first */
|
||
CONTROL_PROTOCOL__ACTION_HEADER_t header;
|
||
uint8_t stream_index;
|
||
} CONTROL_PROTOCOL__FETCH_NEW_DATA_ACTION_t;
|
||
|
||
typedef struct {
|
||
/* Must be first */
|
||
CONTROL_PROTOCOL__ACTION_HEADER_t header;
|
||
uint8_t cluster_index;
|
||
uint8_t lcu_index;
|
||
uint16_t kernel_done_address;
|
||
uint32_t kernel_done_count;
|
||
uint8_t network_index;
|
||
} CONTROL_PROTOCOL__ENABLE_LCU_NON_DEAFULT_ACTION_t;
|
||
|
||
typedef struct {
|
||
/* Must be first */
|
||
CONTROL_PROTOCOL__ACTION_HEADER_t header;
|
||
uint8_t cluster_index;
|
||
uint8_t lcu_index;
|
||
uint8_t network_index;
|
||
} CONTROL_PROTOCOL__ENABLE_LCU_DEFAULT_ACTION_t;
|
||
|
||
typedef struct {
|
||
/* Must be first */
|
||
CONTROL_PROTOCOL__ACTION_HEADER_t header;
|
||
uint8_t cluster_index;
|
||
uint8_t lcu_index;
|
||
} CONTROL_PROTOCOL__DISABLE_LCU_ACTION_t;
|
||
|
||
typedef struct {
|
||
/* Must be first */
|
||
CONTROL_PROTOCOL__ACTION_HEADER_t header;
|
||
uint8_t module_index;
|
||
} CONTORL_PROTOCOL__WAIT_FOR_MODULE_CONFIG_DONE_ACTION_t;
|
||
|
||
typedef struct {
|
||
/* Must be first */
|
||
CONTROL_PROTOCOL__ACTION_HEADER_t header;
|
||
uint8_t h2d_vdma_channel_index;
|
||
uint8_t d2h_vdma_channel_index;
|
||
uint32_t descriptors_per_frame;
|
||
uint16_t programmed_descriptors_count;
|
||
} CONTROL_PROTOCOL__ADD_DDR_PAIR_ACTION_t;
|
||
|
||
typedef struct {
|
||
/* Must be first */
|
||
CONTROL_PROTOCOL__ACTION_HEADER_t header;
|
||
} CONTROL_PROTOCOL__ADD_DDR_BUFFERING_START_ACTION_t;
|
||
|
||
typedef struct {
|
||
/* Must be first */
|
||
CONTROL_PROTOCOL__ACTION_HEADER_t header;
|
||
} CONTROL_PROTOCOL__BURST_CREDITS_TASK_START_ACTION_T;
|
||
|
||
typedef struct {
|
||
CONTROL_PROTOCOL__TRIGGER_t trigger;
|
||
uint16_t triggers_action_count;
|
||
} CONTROL_PROTOCOL__trigger_group_t;
|
||
|
||
typedef CONTROL_PROTOCOL__read_memory_request_t CONTROL_PROTOCOL__read_user_config_request_t;
|
||
typedef CONTROL_PROTOCOL__read_memory_response_t CONTROL_PROTOCOL__read_user_config_response_t;
|
||
typedef CONTROL_PROTOCOL__write_memory_request_t CONTROL_PROTOCOL__write_user_config_request_t;
|
||
|
||
typedef struct {
|
||
uint32_t measurement_enable_length;
|
||
uint8_t measurement_enable;
|
||
} CONTROL_PROTOCOL__idle_time_set_measurement_request_t;
|
||
|
||
typedef struct {
|
||
uint32_t idle_time_ns_length;
|
||
uint64_t idle_time_ns;
|
||
} CONTROL_PROTOCOL__idle_time_get_measurement_response_t;
|
||
|
||
typedef struct {
|
||
uint32_t context_index_length;
|
||
uint8_t context_index;
|
||
uint32_t action_list_offset_length;
|
||
uint16_t action_list_offset;
|
||
} CONTROL_PROTOCOL__download_context_action_list_request_t;
|
||
|
||
#if defined(_MSC_VER)
|
||
// TODO: warning C4200
|
||
#pragma warning(push)
|
||
#pragma warning(disable: 4200)
|
||
#endif
|
||
typedef struct {
|
||
uint32_t base_address_length;
|
||
uint32_t base_address;
|
||
uint32_t is_action_list_end_length;
|
||
uint8_t is_action_list_end;
|
||
uint32_t batch_counter_length;
|
||
uint32_t batch_counter;
|
||
uint32_t action_list_length;
|
||
uint8_t action_list[0];
|
||
} CONTROL_PROTOCOL__download_context_action_list_response_t;
|
||
#if defined(_MSC_VER)
|
||
#pragma warning(pop)
|
||
#endif
|
||
|
||
typedef enum {
|
||
CONTROL_PROTOCOL__CONTEXT_SWITCH_STATUS_RESET = 0,
|
||
CONTROL_PROTOCOL__CONTEXT_SWITCH_STATUS_ENABLED,
|
||
CONTROL_PROTOCOL__CONTEXT_SWITCH_STATUS_PAUSED,
|
||
|
||
/* must be last*/
|
||
CONTROL_PROTOCOL__CONTEXT_SWITCH_STATUS_COUNT,
|
||
} CONTROL_PROTOCOL__CONTEXT_SWITCH_STATUS_t;
|
||
|
||
typedef struct {
|
||
uint32_t state_machine_status_length;
|
||
uint8_t state_machine_status;
|
||
uint32_t application_index_length;
|
||
uint8_t application_index;
|
||
uint32_t dynamic_batch_size_length;
|
||
uint16_t dynamic_batch_size;
|
||
} CONTROL_PROTOCOL__change_context_switch_status_request_t;
|
||
|
||
typedef struct {
|
||
uint32_t interrupt_type_length;
|
||
uint8_t interrupt_type;
|
||
uint32_t interrupt_index_length;
|
||
uint8_t interrupt_index;
|
||
uint32_t interrupt_sub_index_length;
|
||
uint8_t interrupt_sub_index;
|
||
} CONTROL_PROTOCOL__set_dataflow_interrupt_request_t;
|
||
|
||
typedef struct {
|
||
uint32_t application_index_length;
|
||
uint8_t application_index;
|
||
uint32_t dynamic_batch_size_length;
|
||
uint16_t dynamic_batch_size;
|
||
} CONTROL_PROTOCOL__switch_application_request_t;
|
||
|
||
typedef struct {
|
||
uint32_t connection_type_length;
|
||
uint8_t connection_type;
|
||
uint32_t host_ip_address_length;
|
||
uint32_t host_ip_address;
|
||
uint32_t host_port_length;
|
||
uint16_t host_port;
|
||
}CONTROL_PROTOCOL__d2h_event_manager_set_new_host_info_request_t;
|
||
|
||
typedef struct {
|
||
uint32_t priority_length;
|
||
uint8_t priority;
|
||
}CONTROL_PROTOCOL__d2h_event_manager_send_host_info_event_request_t;
|
||
|
||
typedef CONTROL_PROTOCOL__read_memory_request_t CONTROL_PROTOCOL__read_board_config_request_t;
|
||
typedef CONTROL_PROTOCOL__read_memory_response_t CONTROL_PROTOCOL__read_board_config_response_t;
|
||
typedef CONTROL_PROTOCOL__write_memory_request_t CONTROL_PROTOCOL__write_board_config_request_t;
|
||
/* Tightly coupled hailo_device_supported_features_t */
|
||
typedef uint64_t CONTROL_PROTOCOL__supported_features_t;
|
||
|
||
/* Tightly coupled hailo_device_boot_source_t */
|
||
typedef enum {
|
||
CONTROL_PROTOCOL__BOOT_SOURCE_INVALID = 0,
|
||
CONTROL_PROTOCOL__BOOT_SOURCE_PCIE,
|
||
CONTROL_PROTOCOL__BOOT_SOURCE_FLASH
|
||
} CONTROL_PROTOCOL__boot_source_t;
|
||
|
||
/* CONTROL_PROTOCOL_fuse_info_t sturct will be packed to unit_level_tracking_id field in hailo_extended_device_information_t */
|
||
/* CONTROL_PROTOCOL_fuse_info_t size is tightly coupled HAILO_UNIT_LEVEL_TRACKING_BYTES_LEN */
|
||
typedef struct {
|
||
uint8_t lot_id[LOT_ID_BYTES_LEN];
|
||
uint32_t die_wafer_info;
|
||
} CONTROL_PROTOCOL_fuse_info_t;
|
||
|
||
typedef struct {
|
||
uint32_t neural_network_core_clock_rate_length;
|
||
uint32_t neural_network_core_clock_rate;
|
||
uint32_t supported_features_length;
|
||
CONTROL_PROTOCOL__supported_features_t supported_features;
|
||
uint32_t boot_source_length;
|
||
uint32_t boot_source; /*CONTROL_PROTOCOL__boot_source_t*/
|
||
uint32_t lcs_length;
|
||
uint8_t lcs;
|
||
uint32_t soc_id_length;
|
||
uint8_t soc_id[CONTROL_PROTOCOL__SOC_ID_LENGTH];
|
||
uint32_t eth_mac_length;
|
||
uint8_t eth_mac_address[MAC_ADDR_BYTES_LEN];
|
||
uint32_t fuse_info_length;
|
||
CONTROL_PROTOCOL_fuse_info_t fuse_info;
|
||
uint32_t pd_info_length;
|
||
uint8_t pd_info[PM_RESULTS_LENGTH];
|
||
} CONTROL_PROTOCOL__get_extended_device_information_response_t;
|
||
|
||
/* Tightly coupled to hailo_throttling_level_t */
|
||
typedef struct {
|
||
float32_t temperature_threshold;
|
||
float32_t hysteresis_temperature_threshold;
|
||
uint32_t throttling_nn_clock_freq;
|
||
} CONTROL_PROTOCOL__throttling_level_t;
|
||
|
||
/* Tightly coupled to hailo_health_info_t */
|
||
typedef struct {
|
||
uint32_t overcurrent_protection_active_length;
|
||
bool overcurrent_protection_active;
|
||
uint32_t current_overcurrent_zone_length;
|
||
uint8_t current_overcurrent_zone;
|
||
uint32_t red_overcurrent_threshold_length;
|
||
float32_t red_overcurrent_threshold;
|
||
uint32_t orange_overcurrent_threshold_length;
|
||
float32_t orange_overcurrent_threshold;
|
||
uint32_t temperature_throttling_active_length;
|
||
bool temperature_throttling_active;
|
||
uint32_t current_temperature_zone_length;
|
||
uint8_t current_temperature_zone;
|
||
uint32_t current_temperature_throttling_level_length;
|
||
int8_t current_temperature_throttling_level;
|
||
uint32_t temperature_throttling_levels_length;
|
||
CONTROL_PROTOCOL__throttling_level_t temperature_throttling_levels[MAX_TEMPERATURE_THROTTLING_LEVELS_NUMBER];
|
||
uint32_t orange_temperature_threshold_length;
|
||
int32_t orange_temperature_threshold;
|
||
uint32_t orange_hysteresis_temperature_threshold_length;
|
||
int32_t orange_hysteresis_temperature_threshold;
|
||
uint32_t red_temperature_threshold_length;
|
||
int32_t red_temperature_threshold;
|
||
uint32_t red_hysteresis_temperature_threshold_length;
|
||
int32_t red_hysteresis_temperature_threshold;
|
||
} CONTROL_PROTOCOL__get_health_information_response_t;
|
||
|
||
typedef enum {
|
||
CONTROL_PROTOCOL__CONTEXT_SWITCH_BREAKPOINT_CONTROL_SET = 0,
|
||
CONTROL_PROTOCOL__CONTEXT_SWITCH_BREAKPOINT_CONTROL_CONTINUE,
|
||
CONTROL_PROTOCOL__CONTEXT_SWITCH_BREAKPOINT_CONTROL_CLEAR,
|
||
|
||
/* Must be last */
|
||
CONTROL_PROTOCOL__CONTEXT_SWITCH_BREAKPOINT_CONTROL_COUNT
|
||
} CONTROL_PROTOCOL__context_switch_breakpoint_control_t;
|
||
|
||
typedef enum {
|
||
CONTROL_PROTOCOL__CONTEXT_SWITCH_DEBUG_SYS_STATUS_CLEARED = 0,
|
||
CONTROL_PROTOCOL__CONTEXT_SWITCH_DEBUG_SYS_STATUS_WAITING_FOR_BREAKPOINT,
|
||
CONTROL_PROTOCOL__CONTEXT_SWITCH_DEBUG_SYS_STATUS_REACHED_BREAKPOINT,
|
||
|
||
/* Must be last */
|
||
CONTROL_PROTOCOL__CONTEXT_SWITCH_DEBUG_SYS_STATUS_COUNT,
|
||
} CONTROL_PROTOCOL__context_switch_debug_sys_status_t;
|
||
|
||
typedef struct {
|
||
bool break_at_any_application_index;
|
||
uint8_t application_index;
|
||
bool break_at_any_batch_index;
|
||
uint16_t batch_index;
|
||
bool break_at_any_context_index;
|
||
uint8_t context_index;
|
||
bool break_at_any_action_index;
|
||
uint16_t action_index;
|
||
} CONTROL_PROTOCOL__context_switch_breakpoint_data_t;
|
||
|
||
typedef struct {
|
||
uint32_t breakpoint_id_length;
|
||
uint32_t breakpoint_id;
|
||
uint32_t breakpoint_control_length;
|
||
uint8_t breakpoint_control;
|
||
uint32_t breakpoint_data_length;
|
||
CONTROL_PROTOCOL__context_switch_breakpoint_data_t breakpoint_data;
|
||
} CONTROL_PROTOCOL__config_context_switch_breakpoint_request_t;
|
||
|
||
typedef struct {
|
||
uint32_t breakpoint_id_length;
|
||
uint32_t breakpoint_id;
|
||
} CONTROL_PROTOCOL__get_context_switch_breakpoint_status_request_t;
|
||
|
||
typedef struct {
|
||
uint32_t breakpoint_status_length;
|
||
uint8_t breakpoint_status;
|
||
} CONTROL_PROTOCOL__get_context_switch_breakpoint_status_response_t;
|
||
|
||
typedef struct {
|
||
uint32_t is_rma_length;
|
||
uint8_t is_rma;
|
||
} CONTROL_PROTOCOL__enable_debugging_request_t;
|
||
|
||
typedef struct {
|
||
uint32_t main_header_length;
|
||
CONTROL_PROTOCOL__context_switch_main_header_t main_header;
|
||
} CONTROL_PROTOCOL__get_context_switch_main_header_response_t;
|
||
|
||
typedef struct {
|
||
uint32_t batch_index_length;
|
||
uint16_t batch_index;
|
||
uint32_t enable_user_configuration_length;
|
||
uint8_t enable_user_configuration;
|
||
} CONTROL_PROTOCOL__config_context_switch_timestamp_request_t;
|
||
|
||
typedef struct {
|
||
uint32_t dataflow_manager_id_length;
|
||
uint8_t dataflow_manager_id;
|
||
} CONTROL_PROTOCOL__config_stream_response_t;
|
||
|
||
typedef enum {
|
||
CONTROL_PROTOCOL__TOP_MEM_BLOCK_CRYPTO_1 = 0,
|
||
CONTROL_PROTOCOL__TOP_MEM_BLOCK_L4_0_2,
|
||
CONTROL_PROTOCOL__TOP_MEM_BLOCK_L4_1_3,
|
||
CONTROL_PROTOCOL__TOP_MEM_BLOCK_L4_2_4,
|
||
CONTROL_PROTOCOL__TOP_MEM_BLOCK_L4_3_5,
|
||
CONTROL_PROTOCOL__TOP_MEM_BLOCK_SAGE1_CPU_6,
|
||
CONTROL_PROTOCOL__TOP_MEM_BLOCK_SAGE1_CPU_FAST_BUS_7,
|
||
CONTROL_PROTOCOL__TOP_MEM_BLOCK_SAGE1_DEBUG_8,
|
||
CONTROL_PROTOCOL__TOP_MEM_BLOCK_SAGE1_ETH_9,
|
||
CONTROL_PROTOCOL__TOP_MEM_BLOCK_SAGE1_FLASH_10,
|
||
CONTROL_PROTOCOL__TOP_MEM_BLOCK_SAGE1_H264_11,
|
||
CONTROL_PROTOCOL__TOP_MEM_BLOCK_SAGE1_ISP_12,
|
||
CONTROL_PROTOCOL__TOP_MEM_BLOCK_SAGE1_MIPI_RX_13,
|
||
CONTROL_PROTOCOL__TOP_MEM_BLOCK_SAGE1_MIPI_TX_14,
|
||
CONTROL_PROTOCOL__TOP_MEM_BLOCK_SAGE1_PCIE_15,
|
||
CONTROL_PROTOCOL__TOP_MEM_BLOCK_SAGE1_SDIO_16,
|
||
CONTROL_PROTOCOL__TOP_MEM_BLOCK_SAGE1_SOFTMAX_17,
|
||
CONTROL_PROTOCOL__TOP_MEM_BLOCK_SAGE1_USB_18,
|
||
CONTROL_PROTOCOL__TOP_MEM_BLOCK_SAGE1_19,
|
||
/*the cluster ring_s*/
|
||
CONTROL_PROTOCOL__TOP_MEM_BLOCK_SUB_SERVER0_20,
|
||
CONTROL_PROTOCOL__TOP_MEM_BLOCK_SUB_SERVER1_21,
|
||
CONTROL_PROTOCOL__TOP_MEM_BLOCK_SUB_SERVER2_22,
|
||
CONTROL_PROTOCOL__TOP_MEM_BLOCK_SUB_SERVER3_23,
|
||
CONTROL_PROTOCOL__TOP_MEM_BLOCK_SUB_SERVER4_24,
|
||
CONTROL_PROTOCOL__TOP_MEM_BLOCK_SUB_SERVER5_25,
|
||
CONTROL_PROTOCOL__TOP_MEM_BLOCK_SUB_SERVER6_26,
|
||
CONTROL_PROTOCOL__TOP_MEM_BLOCK_SUB_SERVER7_27,
|
||
CONTROL_PROTOCOL__TOP_NUM_MEM_BLOCKS
|
||
} CONTROL_PROTOCOL__biTOP_st_top_mem_block_t;
|
||
|
||
/*only allowing bist on the following memories*/
|
||
#define CONTROL_PROTOCOL__BIST_TOP_WHITELIST ((1 << CONTROL_PROTOCOL__TOP_MEM_BLOCK_L4_0_2) | \
|
||
(1 << CONTROL_PROTOCOL__TOP_MEM_BLOCK_L4_1_3) | \
|
||
(1 << CONTROL_PROTOCOL__TOP_MEM_BLOCK_L4_2_4) | \
|
||
(1 << CONTROL_PROTOCOL__TOP_MEM_BLOCK_L4_3_5))
|
||
|
||
/*only allowing bist on the following memories*/
|
||
#define CONTROL_PROTOCOL__BIST_TOP_BYPASS_ALL_MASK (0x7FFFF)
|
||
|
||
typedef struct {
|
||
uint32_t is_top_test_length;
|
||
bool is_top_test;
|
||
uint32_t top_bypass_bitmap_length;
|
||
uint32_t top_bypass_bitmap;
|
||
uint32_t cluster_index_length;
|
||
uint8_t cluster_index;
|
||
uint32_t cluster_bypass_bitmap_0_length;
|
||
uint32_t cluster_bypass_bitmap_0;
|
||
uint32_t cluster_bypass_bitmap_1_length;
|
||
uint32_t cluster_bypass_bitmap_1;
|
||
} CONTROL_PROTOCOL__run_bist_test_request_t;
|
||
|
||
typedef union {
|
||
CONTROL_PROTOCOL_identify_response_t identity_response;
|
||
CONTROL_PROTOCOL__core_identify_response_t core_identity_response;
|
||
CONTROL_PROTOCOL__read_memory_response_t read_memory_response;
|
||
CONTROL_PROTOCOL__power_measurement_response_t measure_power_response;
|
||
CONTROL_PROTOCOL__set_power_measurement_response_t set_measure_power_response;
|
||
CONTROL_PROTOCOL__get_power_measurement_response_t get_measure_power_response;
|
||
CONTROL_PROTOCOL__examine_user_config_response_t examine_user_config_response;
|
||
CONTROL_PROTOCOL__read_user_config_response_t read_user_config_response;
|
||
CONTROL_PROTOCOL__i2c_read_response_t i2c_read_response;
|
||
CONTROL_PROTOCOL__latency_read_response_t latency_read_response;
|
||
CONTROL_PROTOCOL__sensor_get_config_response_t sensor_get_config_response;
|
||
CONTROL_PROTOCOL__sensor_get_sections_info_response_t sensor_get_sections_info_response;
|
||
CONTROL_PROTOCOL__idle_time_get_measurement_response_t idle_time_get_measurement_response;
|
||
CONTROL_PROTOCOL__download_context_action_list_response_t download_context_action_list_response;
|
||
CONTROL_PROTOCOL__previous_system_state_response_t previous_system_state_response;
|
||
CONTROL_PROTOCOL__get_chip_temperature_response_t get_chip_temperature_response;
|
||
CONTROL_PROTOCOL__read_board_config_response_t read_board_config_response;
|
||
CONTROL_PROTOCOL__get_extended_device_information_response_t get_extended_device_information_response;
|
||
CONTROL_PROTOCOL__get_context_switch_breakpoint_status_response_t get_context_switch_breakpoint_status_response;
|
||
CONTROL_PROTOCOL__get_context_switch_main_header_response_t get_context_switch_main_header_response;
|
||
CONTROL_PROTOCOL__config_stream_response_t config_stream_response;
|
||
CONTROL_PROTOCOL__get_health_information_response_t get_health_information_response;
|
||
CONTROL_PROTOCOL__get_throttling_state_response_t get_throttling_state_response;
|
||
CONTROL_PROTOCOL__get_overcurrent_state_response_t get_overcurrent_state_response;
|
||
// Note: This array is larger than any legal request:
|
||
// * Functions in this module won't write more than CONTROL_PROTOCOL__MAX_CONTROL_LENGTH bytes
|
||
// when recieving a pointer to CONTROL_PROTOCOL__request_parameters_t.
|
||
// * Hence, CONTROL_PROTOCOL__response_parameters_t can be stored on the stack of the calling function.
|
||
uint8_t max_response_size[CONTROL_PROTOCOL__MAX_CONTROL_LENGTH];
|
||
} CONTROL_PROTOCOL__response_parameters_t;
|
||
|
||
typedef union {
|
||
CONTROL_PROTOCOL__read_memory_request_t read_memory_request;
|
||
CONTROL_PROTOCOL__write_memory_request_t write_memory_request;
|
||
CONTROL_PROTOCOL__config_stream_request_t config_stream_request;
|
||
CONTROL_PROTOCOL__open_stream_request_t open_stream_request;
|
||
CONTROL_PROTOCOL__close_stream_request_t close_stream_request;
|
||
CONTROL_PROTOCOL__phy_operation_request_t phy_operation_request;
|
||
CONTROL_PROTOCOL__reset_request_t reset_resquest;
|
||
CONTROL_PROTOCOL__config_core_top_request_t config_core_top_request;
|
||
CONTROL_PROTOCOL__power_measurement_request_t measure_power_request;
|
||
CONTROL_PROTOCOL__set_power_measurement_request_t set_measure_power_request;
|
||
CONTROL_PROTOCOL__get_power_measurement_request_t get_measure_power_request;
|
||
CONTROL_PROTOCOL__start_power_measurement_request_t start_measure_power_request;
|
||
CONTROL_PROTOCOL__i2c_write_request_t i2c_write_request;
|
||
CONTROL_PROTOCOL__i2c_read_request_t i2c_read_request;
|
||
CONTROL_PROTOCOL__write_firmware_update_request_t write_firmware_update_request;
|
||
CONTROL_PROTOCOL__validate_firmware_update_request_t validate_firmware_update_request;
|
||
CONTROL_PROTOCOL__read_user_config_request_t read_user_config_request;
|
||
CONTROL_PROTOCOL__write_user_config_request_t write_user_config_request;
|
||
CONTROL_PROTOCOL__latency_config_request_t latency_config_request;
|
||
CONTROL_PROTOCOL__sensor_store_config_request_t sensor_store_config_request;
|
||
CONTROL_PROTOCOL__sensor_load_config_request_t sensor_load_config_request;
|
||
CONTROL_PROTOCOL__sensor_reset_request_t sensor_reset_request;
|
||
CONTROL_PROTOCOL__sensor_get_config_request_t sensor_get_config_request;
|
||
CONTROL_PROTOCOL__sensor_set_generic_i2c_slave_request_t sensor_set_generic_i2c_slave_request;
|
||
CONTROL_PROTOCOL__context_switch_set_main_header_request_t context_switch_set_main_header_request;
|
||
CONTROL_PROTOCOL__context_switch_set_context_info_request_t context_switch_set_context_info_request;
|
||
CONTROL_PROTOCOL__idle_time_set_measurement_request_t idle_time_set_measurement_request;
|
||
CONTROL_PROTOCOL__download_context_action_list_request_t download_context_action_list_request;
|
||
CONTROL_PROTOCOL__change_context_switch_status_request_t change_context_switch_status_request;
|
||
CONTROL_PROTOCOL__wd_enable_request_t wd_enable_request;
|
||
CONTROL_PROTOCOL__wd_config_request_t wd_config_request;
|
||
CONTROL_PROTOCOL__set_dataflow_interrupt_request_t set_dataflow_interrupt_request;
|
||
CONTROL_PROTOCOL__d2h_event_manager_set_new_host_info_request_t d2h_event_manager_set_new_host_info_request;
|
||
CONTROL_PROTOCOL__d2h_event_manager_send_host_info_event_request_t d2h_event_manager_send_host_info_event_request;
|
||
CONTROL_PROTOCOL__read_board_config_request_t read_board_config_request;
|
||
CONTROL_PROTOCOL__write_board_config_request_t write_board_config_request;
|
||
CONTROL_PROTOCOL__switch_application_request_t switch_application_request;
|
||
CONTROL_PROTOCOL__config_context_switch_breakpoint_request_t config_context_switch_breakpoint_request;
|
||
CONTROL_PROTOCOL__get_context_switch_breakpoint_status_request_t get_context_switch_breakpoint_status_request;
|
||
CONTROL_PROTOCOL__enable_debugging_request_t enable_debugging_request;
|
||
CONTROL_PROTOCOL__set_fw_logger_request_t set_fw_logger_request;
|
||
CONTROL_PROTOCOL__write_second_stage_to_internal_memory_request_t write_second_stage_to_internal_memory_request;
|
||
CONTROL_PROTOCOL__copy_second_stage_to_flash_request_t copy_second_stage_to_flash_request;
|
||
CONTROL_PROTOCOL__set_pause_frames_t set_pause_frames_request;
|
||
CONTROL_PROTOCOL__config_context_switch_timestamp_request_t config_context_switch_timestamp_request;
|
||
CONTROL_PROTOCOL__run_bist_test_request_t run_bist_test_request;
|
||
CONTROL_PROTOCOL__set_clock_freq_request_t set_clock_freq_request;
|
||
CONTROL_PROTOCOL__set_throttling_state_request_t set_throttling_state_request;
|
||
CONTROL_PROTOCOL__sensor_set_i2c_bus_index_t sensor_set_i2c_bus_index;
|
||
CONTROL_PROTOCOL__set_overcurrent_state_request_t set_overcurrent_state_request;
|
||
// Note: This array is larger than any legal request:
|
||
// * Functions in this module won't write more than CONTROL_PROTOCOL__MAX_CONTROL_LENGTH bytes
|
||
// when recieving a pointer to CONTROL_PROTOCOL__request_parameters_t.
|
||
// * Hence, CONTROL_PROTOCOL__request_parameters_t can be stored on the stack of the calling function.
|
||
uint8_t max_request_size[CONTROL_PROTOCOL__MAX_CONTROL_LENGTH];
|
||
} CONTROL_PROTOCOL__request_parameters_t;
|
||
|
||
typedef struct {
|
||
CONTROL_PROTOCOL__request_header_t header;
|
||
uint32_t parameter_count;
|
||
/* Must be last */
|
||
CONTROL_PROTOCOL__request_parameters_t parameters;
|
||
} CONTROL_PROTOCOL__request_t;
|
||
|
||
typedef struct {
|
||
CONTROL_PROTOCOL__response_header_t header;
|
||
uint32_t parameter_count;
|
||
/* Must be last */
|
||
CONTROL_PROTOCOL__response_parameters_t parameters;
|
||
} CONTROL_PROTOCOL__response_t;
|
||
|
||
#pragma pack(pop)
|
||
/* END OF NETWORK STRUCTURES */
|
||
|
||
#define CONTROL_PROTOCOL__MAX_REQUEST_PARAMETERS_LENGTH \
|
||
(CONTROL_PROTOCOL__MAX_CONTROL_LENGTH - offsetof(CONTROL_PROTOCOL__request_t, parameters))
|
||
#define CONTROL_PROTOCOL__MAX_RESPONSE_PARAMETERS_LENGTH \
|
||
(CONTROL_PROTOCOL__MAX_CONTROL_LENGTH - offsetof(CONTROL_PROTOCOL__response_t, parameters))
|
||
|
||
#define CONTROL_PROTOCOL__ACTION_LIST_RESPONSE_MAX_SIZE \
|
||
(CONTROL_PROTOCOL__MAX_RESPONSE_PARAMETERS_LENGTH - sizeof(CONTROL_PROTOCOL__download_context_action_list_response_t))
|
||
|
||
/* Context switch structs - as it's used by the control.c file and inter cpu control */
|
||
#define CONTROL_PROTOCOL__CONTEXT_NETWORK_DATA_SINGLE_CONTROL_MAX_SIZE \
|
||
(CONTROL_PROTOCOL__MAX_REQUEST_PARAMETERS_LENGTH - sizeof(CONTROL_PROTOCOL__context_switch_set_context_info_request_t))
|
||
|
||
typedef struct {
|
||
bool is_first_control_per_context;
|
||
bool is_last_control_per_context;
|
||
uint8_t cfg_channels_count;
|
||
CONTROL_PROTOCOL__host_buffer_info_t config_buffer_infos[CONTROL_PROTOCOL__MAX_CFG_CHANNELS];
|
||
CONTROL_PROTOCOL__stream_remap_data_t context_stream_remap_data;
|
||
uint8_t number_of_edge_layers;
|
||
uint8_t number_of_trigger_groups;
|
||
uint32_t context_network_data_length;
|
||
uint8_t context_network_data[CONTROL_PROTOCOL__CONTEXT_NETWORK_DATA_SINGLE_CONTROL_MAX_SIZE];
|
||
} CONTROL_PROTOCOL__context_switch_context_info_single_control_t;
|
||
|
||
/* Context switch user structs */
|
||
|
||
#define CONTROL_PROTOCOL__CONTEXT_NETWORK_DATA_MAX_SIZE (8 * 1024)
|
||
|
||
typedef struct {
|
||
uint8_t interrupt_type;
|
||
uint8_t interrupt_index;
|
||
uint8_t interrupt_sub_index;
|
||
} CONTROL_PROTOCOL__dataflow_interrupt_t;
|
||
/* End of context switch structs */
|
||
|
||
typedef enum {
|
||
CONTROL_PROTOCOL__MESSAGE_TYPE__REQUEST = 0,
|
||
CONTROL_PROTOCOL__MESSAGE_TYPE__RESPONSE,
|
||
} CONTROL_PROTOCOL__message_type_t;
|
||
|
||
typedef enum {
|
||
CONTROL_PROTOCOL__COMMUNICATION_TYPE_UDP = 0,
|
||
CONTROL_PROTOCOL__COMMUNICATION_TYPE_MIPI,
|
||
CONTROL_PROTOCOL__COMMUNICATION_TYPE_PCIE,
|
||
CONTROL_PROTOCOL__COMMUNICATION_TYPE_INTER_CPU,
|
||
|
||
/* Must be last! */
|
||
CONTROL_PROTOCOL__COMMUNICATION_TYPE_COUNT
|
||
} CONTROL_PROTOCOL__communication_type_t;
|
||
|
||
typedef enum {
|
||
CONTROL_PROTOCOL__RESET_TYPE__CHIP = 0,
|
||
CONTROL_PROTOCOL__RESET_TYPE__NN_CORE,
|
||
CONTROL_PROTOCOL__RESET_TYPE__SOFT,
|
||
CONTROL_PROTOCOL__RESET_TYPE__FORCED_SOFT,
|
||
|
||
/* Must be last! */
|
||
CONTROL_PROTOCOL__RESET_TYPE__COUNT
|
||
} CONTROL_PROTOCOL__reset_type_t;
|
||
|
||
|
||
typedef union {
|
||
/* Needed in order to parse unknown header */
|
||
CONTROL_PROTOCOL__common_header_t common;
|
||
|
||
CONTROL_PROTOCOL__request_header_t request;
|
||
CONTROL_PROTOCOL__response_header_t response;
|
||
} CONTROL_PROTOCOL__message_header_t;
|
||
|
||
#ifdef __cplusplus
|
||
}
|
||
#endif
|
||
|
||
#endif /* __CONTROL_PROTOCOL_H__ */
|